Electro-thermal nested die-attach design

Details Electro-thermal nested die-attach design Electro-thermal nested die-attach design

1997-10-15

2000-08-01

Williams, Alexander O.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Configuration or pattern of bonds

257790, 257782, 257783, 257668, 29834, 29840, 29841, 361719, 361770, 361771, 174260, H05K 332, H05K 1304, H01L 2329, H01L 2348

Patent

active

060970995

ABSTRACT:
A design having a semiconductor microchip bonded to a circuit board is described. This design may include: a printed circuit board (58); a semiconductor microchip (56) bonded to the circuit board (58) by means of an adhesive layer placed between the bonding surface of the microchip (56) and the desired bonding site on the circuit board (58); the adhesive layer providing for thermal relief as well as electrical contact between the microchip (56) and circuit board (58), and consisting of two or more concentric regions that adjoin but do not overlap one another; one being a center core region (50) of thermally and electrically conductive material; the other being a perimeter region (54) of thermally conductive and electrically nonconductive material surrounding the center core region (50) such that the perimeter region's (54) inner boundary completely bounds the center core region (50); and such that the perimeter region's (54) outer boundary extends to a lead on the microchip (56). Other devices, systems, and methods are also disclosed.

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