Electrically writable and erasable read-only memory cell arrange

Details Electrically writable and erasable read-only memory cell arrange Electrically writable and erasable read-only memory cell arrange

1997-11-06

1999-08-24

Chaudhuri, Olik

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

257315, 257622, H01L 29788, H01L 2906

Patent

active

059435720

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

Read-only memory cell arrangements having electrically writable and electrically erasable read-only memory cells using silicon technology, so-called flash EEPROMs, are required for many applications. These flash EEPROM arrangements retain the stored data even without a voltage supply.
In technical terms, these memory cells are mainly realized by an MOS transistor, which has, on the channel region, a first dielectric, a floating gate, a second dielectric and a control gate. If a charge is stored on the floating gate, then it influences the threshold voltage of the MOS transistor. In such a memory cell arrangement, the state "charge on the floating gate" is assigned to a first logic value and the state "no charge on the floating gate" is assigned to a second logic value. The information is written to the memory cells by means of a Fowler/Nordheim tunnelling current, by which electrons are injected onto the floating gate. The information is erased by a tunnelling current in the opposite direction through the first dielectric.
In memory cell arrangements of this type, the MOS transistors are constructed as planar MOS transistors and are arranged in a planar cell architecture. As a result, the theoretical minimum area requirement of a memory cell is 4F.sup.2, where F is the smallest structure size that can be produced with the respective technology. Flash EEPROM arrangements of this type are currently offered for volumes of data of at most 64 Mbits.
Larger volumes of data can currently be stored in a writable and erasable manner only in dynamic memory cell arrangements (DRAM) or on magnetic data media. A DRAM continually requires a voltage supply in order to retain the stored data. Magnetic data media, on the other hand, are based on mechanical systems with rotating storage media.
The invention is based on the problem of specifying an electrically writable and erasable read-only memory cell arrangement which can be produced with a smaller area requirement for each memory cell. It is furthermore intended to specify a method for the production of such a memory cell arrangement.


SUMMARY OF THE INVENTION

This problem is solved according to the invention by means of an electrically writable and erasable read-only memory cell.
In general terms the present invention is an electrically writable and erasable read-only memory cell arrangement. A multiplicity of individual memory cells are provided in a region, doped by a first conductivity type, of a semiconductor substrate. The region doped by the first conductivity type is insulated from the semiconductor substrate. The memory cells are in each case arranged in rows which run essentially parallel. Longitudinal trenches, which run essentially parallel to the rows, are provided in a main area of the semiconductor substrate. The rows are in each case arranged alternately on the main area between adjacent longitudinal trenches and on the bottom of the longitudinal trenches. The memory cells each comprise at least one MOS transistor having source/drain regions which are doped by a second conductivity type opposite to the first, a first dielectric, a floating gate, a second dielectric and a control gate. Word lines, which are each connected to the control gates on MOS transistors arranged along different rows, run transversely with respect to the rows.
Advantageous developments of the present invention are as follows.
A heavily doped, p.sup.+ -doped layer is provided at the level of half the trench depth for the purpose of insulation between adjacent rows. The MOS transistors of memory cells arranged along a row are interconnected in series. The interconnected source/drain regions of MOS transistors, which are adjacent along a row, are constructed as a coherent doped region in the semiconductor substrate. Each row has two connections, between which the MOS transistors arranged in the row are interconnected in series.
The sides of the longitudinal trenches have bulges in the region of the trench bottom which are filled with insulating material.

REFERENCES:
patent: 4814840 (1989-03-01), Kameda
patent: 5306941 (1994-04-01), Yoshida
patent: 5485027 (1996-01-01), Williams et al.
patent: 5514890 (1996-05-01), Yang et al.
patent: 5610419 (1997-03-01), Tanaka
Academic Press, Inc., (1984), vol. 8, Plasma Processing for VLSI, Edited by Norman G. Einspruch et al, VLSI Electronics Microstructure Science, pp. 124-127.

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