Electrically programmable memory cell configuration

Details Electrically programmable memory cell configuration Electrically programmable memory cell configuration

1999-02-26

2000-09-12

Tran, Minh Loan

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257314, 257315, 257316, 257328, 257329, 257330, H01L 2976, H01L 29788

Patent

active

061181595

ABSTRACT:
The memory cell configuration comprises vertical transistors which are connected in a NOR architecture. The vertical transistors are disposed on flanks of trenches. Each vertical transistor includes an electrically insulated floating gate electrode, whose charge can be varied by Fowler-Nordheim tunneling due to a voltage drop between a control gate electrode and a source/drain region. The length of a coupling area in a direction parallel to a channel width, between the control gate electrode and the floating gate electrode is less than the channel width, in order to reduce the operating voltage. This is achieved by thermal oxidation of parts of the flanks of the trenches. Transistors which are adjacent in a direction transverse to the trenches share bit lines. Each bit line has a lightly doped first part and a highly doped second part. The coupling area can be enlarged even further by using a strip-shaped mask, which is extended by spacers.

REFERENCES:
patent: 5053840 (1991-10-01), Yoshikawa
"A New Cell Structure for Sub-Quarter Micron High Density Flash Memory" (Yamauchi et al.), IEDM, 1995, pp. 267-270.
"A Novel NOR Virtual-Ground Array Architecture For High Density Flash" (Yamauchi et al.), 1996 International Conference on Solid State Devices and Materials, pp. 269-271; 1996.
"A 0.54.beta.m.sup.2 Self-Aligned, HSG Floating Gate Cell (SAHF Cell) for 256Mbit Flash Memories" (Shirai et al.), IEDM 1995, pp. 653-656; 1995.
German Published Application No. 195 244 478.8 (Hofmann et al.), dated Jul. 5, 1995, electrically erasable read-only memory cell configuration.

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