Electrically erasable programmable read-only memory (EEPROM)...

Details Electrically erasable programmable read-only memory (EEPROM)... Electrically erasable programmable read-only memory (EEPROM)...

1999-10-26

2002-11-19

Booth, Richard (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S258000

Reexamination Certificate

active

06483145

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to integrated circuit memory devices and fabrication methods therefor, and more particularly to EEPROM memory devices and methods of fabricating the same.
BACKGROUND OF THE INVENTION
EEPROMs are nonvolatile memory devices that are electrically programmable. For electrical reprogrammability, an EEPROM can use a mechanism known as Fowler-Nordheim tunneling, also referred to as electron tunneling, or simply tunneling. Fowler-Nordheim tunneling is a quantum mechanical effect which allows electrons to pass through an energy barrier at a silicon-silicon dioxide interface at a lower energy than the 3.2 eV that is generally required to pass over this energy barrier.
Flash-type EEPROMs may include a one-transistor storage cell. Other types of EEPROMs may include a two-transistor storage cell. The basic two-transistor storage cell includes an access or select transistor and a double polysilicon storage or sense transistor. The sense transistor includes a floating polysilicon gate that is isolated in silicon dioxide, and that is capacitively coupled to a second polysilicon control gate that is stacked above it. The floating gate tunneling oxide cell is often referred to as a FLoating gate Tunnel OXide or FLOTOX-type of EEPROM. An overview of EEPROMs is provided in Chapter 12 of the textbook entitled
Semiconductor Memories
, pp. 609-650, the disclosure of which is hereby incorporated herein by reference.
FIG. 1
is a cross-sectional view of a first conventional FLOTOX-type EEPROM memory cell. As shown in
FIG. 1
, a thin tunnel insulating layer
16
and a thick gate insulating layer
12
are formed on an integrated circuit substrate
10
, such as a monocrystalline silicon substrate. A sense transistor gate I is a multilayered structure including a floating gate
18
, an interlevel insulating layer
20
and a sense gate
22
on the tunnel insulating layer
16
and on a portion of the gate insulating layer
12
. A select transistor gate II includes a single select gate layer
24
on the gate insulating layer
12
and spaced apart from the sense transistor gate I.
Continuing with the description of
FIG. 1
, a doped region
14
extends from beneath the tunnel insulating layer
16
to beneath the select transistor gate II. A second doped region, also referred to as a source region
26
, is spaced apart from the first doped region
14
and extends from beneath the sense gate I to outside the sense gate. Finally, a third doped region
28
is spaced apart from the first and second doped regions
14
and
26
, and extends from beneath the select gate II to outside the select gate II. Each of the first, second and third doped regions
14
,
26
and
28
preferably forms a semiconductor junction with the substrate
10
.
The floating gate
18
may be fabricated from a first polysilicon layer and the sense gate
22
and the select gate layer
24
may be fabricated from a second polysilicon layer. As also shown in
FIG. 1
, the sense gate
22
may be narrower than the floating gate
18
. EEPROM cells according to
FIG. 1
may be fabricated by patterning a first polysilicon layer to fabricate the floating gate
18
. Then, the sense gate
22
and the single select gate layer
24
may be patterned from a second polysilicon layer in a second photolithography process. Unfortunately, in such a process, it may be difficult to align the sense gate
22
to the floating gate
18
when the size of the memory cell is decreased. Moreover, short circuits may be produced by residual polysilicon material that is generated when etching the second polysilicon layer, which can reduce process reliability.
FIG. 2
is a cross-sectional view of another conventional EEPROM storage cell. In the device of
FIG. 2
, the floating gate
58
a
and the sense gates
62
a
that form the sense transistor gate I are separated into two spaced apart portions. Moreover, the select transistor gate II may be formed from two layers of polysilicon
58
b
and
62
b
that are separated by an interlevel insulating layer
60
, and that may be electrically interconnected, for example using a suitable buried contact or other means well known to those having skill in the art. The sense transistor gate I and the select transistor gate II may be formed in a one step etching process by etching a second polysilicon layer
62
, an interlevel insulating layer
60
and a first polysilicon layer
58
in sequence. A first doped region
54
is formed beneath the tunnel insulating layer
56
and beneath the gate insulating layer
52
in the integrated circuit substrate
50
. Second and third (source and drain) doped regions
64
and
66
also may be formed. See U.S. Pat. No. 4,477,825 to Yaron et al.
In the EEPROM cell of
FIG. 2
, alignment of the sense gate
62
a
to the floating gate
58
a
may be improved, since a single photolithography step may be used. However, since the floating gates
58
a
and the sense gates
62
a
are separated, the unit cell size may be larger than the device of FIG.
1
. Accordingly, it may be difficult to form highly integrated EEPROM devices using the unit cell of FIG.
2
.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved EEPROM devices and methods of fabricating the same.
It is another object of the present invention to provide EEPROM devices and fabrication methods that can provide improved alignment between the floating gate and the sense gate thereof.
It is still another object of the present invention to provide EEPROM devices and fabrication methods that can be highly integrated with high reliability.
These and other objects can be provided, according to the present invention, by EEPROM devices that include a gate insulating layer and a tunnel insulating layer that is thinner than the gate insulating layer, on an integrated circuit substrate, and a sense transistor gate on the tunnel insulating layer and on the gate insulating layer. The sense transistor gate comprises a floating gate on the tunnel insulating layer and on the gate insulating layer, a first interlevel insulating layer on the floating gate opposite the tunnel insulating layer and the gate insulating layer, and a sense gate on the first interlevel insulating layer opposite the floating gate. A select transistor gate also is included on the gate insulating layer and spaced apart from the sense transistor gate. The select transistor gate comprises a first select gate on the gate insulating layer that is spaced apart from the sense transistor gate, a second interlevel insulating layer on the first select gate opposite the gate insulating layer, and a second select gate on the second interlevel insulating layer opposite the first select gate that is spaced apart from the sense gate.
EEPROM devices according to the present invention also include first, second and third doped regions in the integrated circuit substrate. The first doped region is beneath the tunnel insulating layer and extends to beneath the select transistor gate. The second doped region is beneath the sense transistor gate and is spaced apart from the first doped region. The third doped region is beneath the select transistor gate and is spaced apart from the first doped region.
The floating gate and the first select gate preferably comprise respective first and second portions of a first layer, and the sense gate and the second select gate preferably comprise respective first and second portions of a second layer. The first and second layers preferably comprise polysilicon and may comprise polycide. The first and second interlevel insulating layer also preferably are first and second portions of a third layer that preferably comprises oxide such as silicon dioxide and/or silicon oxynitride.
The first, second and third doped regions also may include lightly doped and heavily doped portions. In particular, the first doped region may comprise a first portion that extends from beneath the tunnel insulating layer to outside the sense transistor gate, and a second portion that extends from the first portion

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