Electrically erasable non-volatile memory

Details Electrically erasable non-volatile memory Electrically erasable non-volatile memory

2000-05-10

2001-07-03

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S261000

Reexamination Certificate

active

06255172

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a structure of a memory and a method of manufacturing the same, and more particularly to a structure of an electrically erasable non-volatile memory and a method of manufacturing the same.
2. Description of the Related Art
A non-volatile memory which can still keep data stored therein even without any power source supplied, operates at a high speed and has a small volume and is shock proof, is worldwide used. In order to add, delete data, an electrically erasable nonvolatile memory is developed. All electrically erasable non-volatile memories have the same operational principle. That is, data can be amended by injecting/pulling out electrons into/from a floating gate thereby to control the channel between source and drain under the floating gate on and off. In other words, the turned-on or off channel indicates that one-bit data stored is “0” or “1.”
One of electrically erasable non-volatile memories can store/erase data using a floating gate, a control gate and a select transistor. The operation of this electrically erasable non-volatile memory will be described in the following. To inject electrons into the floating gate (i.e., Channel Hot Electron Injection, CHEI), the electrically erasable non-volatile memory is first turned on through the control gate. Simultaneously, a high voltage is applied on the drain region to increase electron impacts thereby to generate a great amount of hot electrons. The hot electrons has high enough energy to pass through a tunnel oxide layer and then stay in the floating gate. Next, if it needs to pull out electrons stored in the floating gate, a high negative voltage must be applied on the control gate to thereby pull out the electrons to source using tunneling effect. The elect transistor can prevent the electrons from being excessively pull out. Therefore, the floating gate will not bring positive charges to cause a current leakage problem.
Referring to FIGS.
1
A-ID, a method of manufacturing an electrically erasable nonvolatile memory is shown. Fist, in
FIG. 1A
, a substrate
100
having a tunnel oxide layer
110
and a polysilicon floating gate
120
already formed thereon is provided. In
FIG. 1B
, a silicon oxide layer
130
, a silicon nitride layer
132
and a silicon oxide layer
134
(known as a structure of ONO) are formed on the substrate
100
. Then, a polysilicon layer
140
is formed on the silicon oxide layer
134
as shown in FIG.
1
C.
Thereafter, in
FIG. 1D
, the polysilicon layer
140
is patterned to form a control gate
140
a
and a select transistor gate
140
b
. The control gate
140
a
is located above the floating gate
120
with the ONO layer therebetween. The select transistor gate
140
b
is located on both sides of the floating gate
120
above the substrate
100
also with the ONO layer therebetween. Then, using the select transistor gate
140
b
as a mask, the silicon oxide layer
134
, the silicon nitride layer
132
, the silicon oxide layer
130
are etched to form a dielectric layer consisting of a silicon oxide layer
130
a
, a silicon nitride layer
132
a
and a silicon oxide
134
a
(ONO). Finally, ion implantation is performed on the substrate
100
to form source and drain regions
150
on both sides of the silicon oxide layer
130
a.
In the prior art, the reason of using the ONO layer as a dielectric layer between the control gate
140
a
and the floating gate
120
is to increase the capacitance between the control gate
140
a
and the floating gate
120
to thereby increase the control gate coupling ratio and to decrease the operation voltage. The principle of increasing the capacitance using the ONO structure will be described in the following.
First, the silicon nitride layer
132
a
has a better capability of stopping electrons, and therefore, the dielectric layer including the silicon nitride layer can be thinner. Since silicon nitride has a great dielectric constant, the dielectric constant of the dielectric layer including the silicon nitride layer
132
a
can also be increased. Since the dielectric layer has a decreased thickness and an increased dielectric constant, the capacitance between the control gate
140
a
and the floating gate
120
is increased. Furthermore, since the silicon nitride layer
132
a
has a poor adhesive force with the control gate
140
a
and the floating gate
120
formed of ploysilicon, the silicon oxide layers
130
a
,
134
a
having a better adhesive force can be used between the silicon nitride layer
132
a
, the control gate
140
a
, and the floating gate
120
thereby to form a structure of ONO. However, the conventional electrically erasable non-volatile memory has the following problems.
First, since the volume of the device is further shrunk, the thickness of the ONO structure between the control gate
140
a
and the floating gate
120
must be decreased so as to maintain a proper control gate coupling ratio. This causes that the threshold voltage of the select transistor consisting of the select transistor gate
140
b
, the ONO layer under the select transistor gate and the substrate is reduced, too, resulting in a poor capability of preventing hot electrons from being excessively pull out. Therefore, if the volume of the device is shrunk, the control gate coupling ratio and the select transistor must be taken into account. This will cause the development of the device limited. Moreover, since it is easy for electrons to be captured in the silicon nitride
132
under a high voltage, the threshold voltage of the select transistor becomes unstable. This will cause that the device can not be easily controlled.
SUMMARY OF THE INVENTION
In view of the above, the invention is to provide a method of manufacturing an electrically erasable non-volatile memory for resolving the problem that the function of the select transistor is affected by the ONO structure as stated in the prior art.
A method of manufacturing an electrically erasable non-volatile memory includes the following steps. First, a substrate having a tunnel oxide layer formed thereon is provided. A first conductive layer and a silicon oxide/silicon nitride/silicon oxide layer are formed in order on the tunnel oxide layer. The silicon oxide/silicon nitride/silicon oxide layer and the first conductive layer are patterned, wherein the residual first conductive layer serves as a floating gate. A first oxide layer is formed on the sidewalls of the floating gate. A silicon nitride spacer is formed on the side walls of the first oxide layer. A second oxide layer is formed above the substrate. An oxidation reaction is performed to form a third oxide layer on the substrate on both sides of the silicon nitride spacer. A patterned second conductive layer consisting of a control gate and a select transistor gate which are electrically coupled to each other is formed, wherein the control gate is located on the second oxide layer above the floating gate, and the select transistor gate is located on the third oxide layer on both sides of the floating gate. The exposed part of the third oxide layer is removed to thereby form a gate oxide under the select transistor gate. Ion implantation is performed on the substrate to form source/drain regions in the substrate on both sides of the gate oxide layer.
As described above, the thickness of the gate oxide layer of the select transistor is additionally increased using thermal oxidation in the present invention. Therefore, when the volume of the device is shrunk, the thickness of the ONO structure can be reduced to maintain a proper control gate coupling ratio, and the thickness of the gate oxide layer can be adjusted to an optimized value. Furthermore, the surface of the floating gate is protected by the silicon nitride layer of the ONO structure from being oxidized when the thickness of the gate oxide layer of the select transistor is additionally increased by oxidation. Therefore, the thickness of the ONO structure can not be increased due to oxidation.
Moreover, Since the gate dielectric la

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