Electrically erasable and programmable non-volatile memory cell

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S314000

Reexamination Certificate

active

06876033

ABSTRACT:
An electrically erasable and programmable memory cell is provided. The memory cell includes a floating gate MOS transistor and a bipolar transistor for injecting an electric charge into the floating gate. The floating gate transistor has a source region and a drain region formed in a first well with a channel defined between the drain and source regions, a control gate region, and a floating gate extending over the channel and the control gate region. The bipolar transistor has an emitter region formed in the first well, a base region consisting of the first well, and a collector region consisting of the channel. The memory cell includes a second well that is insulated from the first well, and the control gate region is formed in the second well. Further embodiments of the present invention provide a memory including at least one such memory cell, an electronic device including such a memory, and methods of integrating a memory cell and erasing a memory cell.

REFERENCES:
patent: 5872732 (1999-02-01), Wong
patent: 5896315 (1999-04-01), Wong
patent: 5936276 (1999-08-01), Maurelli et al.
patent: 6013552 (2000-01-01), Oyama
patent: 6025625 (2000-02-01), Chi
patent: 6277689 (2001-08-01), Wong
patent: 1091408 (2001-04-01), None
patent: WO 9847150 (1998-10-01), None
European Search Report for European Application No. 02425416.

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