Electrically conductive substrate interconnect continuity region

Details Electrically conductive substrate interconnect continuity region Electrically conductive substrate interconnect continuity region

1997-10-20

1999-01-12

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438525, H01L 21265

Patent

active

058588450

ABSTRACT:
The invention is a semiconductor memory structure having an electrically conductive substrate interconnect formed to provide electrical continuity between a buried contact region and a source/drain region of a transistor without overlap of the buried contact region with the source/drain region. The electrically conductive substrate interconnect is formed during an ion bombardment of the substrate wherein the ions enter the substrate at an oblique angle and underlie at least a portion of a region utilized to control the amount of ions entering the substrate.

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