Electrically blowable fuse with reduced cross-sectional area

Details Electrically blowable fuse with reduced cross-sectional area Electrically blowable fuse with reduced cross-sectional area

2001-01-26

2003-04-15

Wong, Don (Department: 2821)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S128000, C438S333000, C438S589000, C257S529000

Reexamination Certificate

active

06548358

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to fuses included within semiconductor structures which protect semiconductor devices from excessive voltage and/or current or which selectively and permanently connect/disconnect semiconductor devices from one another.
2. Description of the Related Art
As the size and voltage/current ratings of semiconductor devices becomes smaller, as a result of device miniaturization, the fuses which protect or disconnect such devices must be opened (“blown”) with smaller voltages and currents. In an effort to reduce the minimum current/voltage required to open a fuse, conventional fuse structures have a reduced cross-sectional area and have bends in the conductive path to create current crowding. Such structures create a localized high resistance fuse region which causes the fuse to open with smaller voltages and currents.
FIG. 1A
illustrates a top view of a conventional current-blow fuse. To reduce the fuse-opening current requirements, conventional fuses make the width of the fuse element (Wf)
10
as small as possible, and make the width of the interconnect conductor (W
0
)
11
at the end of the fuse as large as possible relative to the length of the fuse element (Lf)
12
.
These dimensions result in the fuse resistance being substantially higher than the resistance of the interconnect conductor
11
. Furthermore, the step in conductor width (W
0
vs. Wf) results in current crowding at the junction of the fuse and the relatively wide interconnect conductor
11
. Current crowding also increases the resistance of the fuse and reduces the current required to open the fuse.
This effect is illustrated by the top view of the region
13
where conductive wiring
11
connects to the fusible link
10
in FIG.
1
B. Within the region
13
where current crowding occurs, localized heating is increased. This makes it likely that the fuse will open at this point, when it is desired to be blown. The step in conductor width between conductive wiring and the fusible link, improves the consistency of the location at which the fuse will open. This results in a tighter distribution of blow-current compared to fuses having constant width.
Reduction of the fuse-opening current is important because it allows the size of the fuse drivers to be reduced, resulting in a tight fuse pitch, and allows fuses to be opened with lower voltages.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a fuse and method for making a fuse which is electrically blowable with normal operating power supply voltages and which allows redundancy and other circuit customization to be implemented at the module level.
The inventive fuse includes a localized high resistance region which creates a temperature high enough to open the fuse with normal operating voltages. Furthermore, the inventive fuse can be fabricated with the standard existing processing steps and is compatible with present dynamic random access memory (DRAM) technologies.
Briefly, the invention includes a semiconductor fuse positioned between conductors for connecting at least two wiring lines. The fuse comprises spacers positioned on adjacent ones of the conductors, and a fuse element positioned between the spacers and connected to the wiring lines. A space between the conductors comprises a first width comprising a smallest possible photolithographic width and the fuse element has a second width smaller than the first width.
The conductors comprise gate conductor stacks. The fuse element is opened with internal operating currents and voltages of the wiring lines. The spacers comprise nitride spacers and the fuse element comprises polysilicon. The fuse element may include a bend. The fuse may also include a void above the fuse element.
The invention also includes a method of forming a semiconductor fuse between at least two conductors and for connecting at least two wiring lines, the method comprising steps of forming spacers on adjacent ones of the conductors, forming a fuse element between the spacers, and connecting the fuse element to the wiring lines.
The invention also includes multiple steps of etching a trench between adjacent ones of the conductors, such that the trench is wider in a top portion than in a bottom portion. The step of forming the fuse element comprises steps of filing the trench with a conductive material, wherein the conductive material has a width dependent etch rate, etching the conductive material, such that the conductive material remains in the bottom portion and is removed from the top portion.
A different embodiment of the invention includes conductors, each of the conductors having a conductive layer and an insulating layer above the conductive layer, wherein a first width between the conductive layers of adjacent conductors is greater than a second width between the insulating layers of the adjacent conductors, first spacers positioned on the insulating layer and the conductive layer of adjacent ones of the conductors, a fuse element positioned between the first spacer of adjacent ones of the conductors and connected to the wiring lines, and second spacers positioned between the fuse element and the first spacers, the second spacers being on a same layer level as the conductive layer, wherein a difference between the first width and the second width is occupied by the second spacers. The second spacers increase thermal insulation of the fuse.
Correspondingly, the invention also includes a method of forming a semiconductor device for connecting at least two wiring lines. The method comprises steps of forming at least two conductors by depositing a conductive layer, depositing an insulating layer above the conductive layer, and etching the conductive layer and the insulating layer to form a trench between adjacent ones of the conductors, undercutting the conductive layer under the insulating layer, forming conformal first spacers on the insulating layer and the conductive layer in the trench, forming second spacers in the trench on the first spacers at a same layer level as the conductive layer, such that an area of the trench equal to an amount of the undercutting is occupied by the second spacers, and filling the trench with a fuse element, the fuse element covering the first spacers and the second spacers. The step of forming the second spacers comprises a step of increasing thermal insulation of the fuse element.
Another embodiment of the invention includes a semiconductor wiring structure positioned between at least two conductors and comprises spacers positioned on adjacent ones of the conductors, and at least one wiring element positioned between the spacers. The conductors comprise gate conductor stacks.
The invention correspondingly includes a method of forming a semiconductor wiring between at least two conductors comprising steps of forming spacers on adjacent ones of the conductors and forming at least one wiring element between the spaces. The conductors comprise gate conductor stacks. The wiring elements have twice the pitch of the maximum possible lithographic wiring pitch. The wiring density of the composite wiring elements and conductors is twice that of wiring produced by conventional lithographic means.
Another embodiment of the invention is a semiconductor resistor/capacitor circuit which comprises a plurality of conductors, spacers positioned on adjacent ones of the conductors, and a capacitive element positioned between the spacers. The conductors comprise gate conductor stacks and act as a resistive element.
The invention correspondingly includes a method of forming a semiconductor resistor/capacitor comprising steps of forming at least two conductors, forming spacers on adjacent ones of the conductors, and forming a capacitive element between the conductors. The conductors comprise gate conductor stacks and act as a resistive element.


REFERENCES:
patent: 4647340 (1987-03-01), Sziuk et al.
patent: 5011791 (1991-04-01), Mastroianni
patent: 5282158 (1994-01-01), Lee
patent: 5331196 (1994-07-01)

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