Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-07-12
2009-02-17
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S643000
Reexamination Certificate
active
07491642
ABSTRACT:
Electrical structures and devices may be formed and include an organic passivating layer that is chemically bonded to a silicon-containing semiconductor material to improve the electrical properties of electrical devices. In different embodiments, the organic passivating layer may remain within finished devices to reduce dangling bonds, improve carrier lifetimes, decrease surface recombination velocities, increase electronic efficiencies, or the like. In other embodiments, the organic passivating layer may be used as a protective sacrificial layer and reduce contact resistance or reduce resistance of doped regions. The organic passivation layer may be formed without the need for high-temperature processing.
REFERENCES:
patent: 3832700 (1974-08-01), Wu et al.
patent: 3961353 (1976-06-01), Aboaf et al.
patent: 4106951 (1978-08-01), Masi
patent: 4461691 (1984-07-01), Frank
patent: 4608097 (1986-08-01), Weinberger et al.
patent: 4960722 (1990-10-01), Ogawa
patent: 5304583 (1994-04-01), Ogawa
patent: 5360759 (1994-11-01), Stengl et al.
patent: 5429708 (1995-07-01), Linford et al.
patent: 5599742 (1997-02-01), Kadomura
patent: 5972724 (1999-10-01), Arndt et al.
patent: 6147405 (2000-11-01), Hu
patent: 6197668 (2001-03-01), Gardner et al.
patent: 6312581 (2001-11-01), Bruce et al.
patent: 42 29 031 (1994-03-01), None
patent: 54-76629 (1979-06-01), None
patent: 63-161672 (1988-07-01), None
patent: 6-84852 (1994-03-01), None
patent: 06084852 (1994-03-01), None
Translation of JP 6-84852 A.
Wolf, et al. Silicon Processing for the VLSI Era, vol. 1-Process Technology, Lattice Press: Sunset Beach CA, 1986, p. 5.
Bansal et al. “Alkylation of Si surfaces using a two-step halogenation/Grignard route” Journal of the American Chemical Society, vol. 118, 1996, pp. 7225-7226.
Ikawa et al., “A New Surface Protecting Layer for Si Substrate Preventing Surface Oxidation,” J. Electrochem. Soc., vol. 138, No. 8 pp. 2382-2386, Aug. 1991.
Wolf, Stanley and Tauber, Richard N., “Silicon Processing for the VLSI Era: Process Technology,” Lattice Press: Sunset Beach, CA. pp. 264-267 (1986).
Lewis Nathan S.
Royea William
Baker, Jr. Joseph R.
Gavrilovich Dodd & Lindsey LLP
Jr. Carl Whitehead
Rodgers Colleen E
The California Institute of Technology
LandOfFree
Electrical passivation of silicon-containing surfaces using... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Electrical passivation of silicon-containing surfaces using..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electrical passivation of silicon-containing surfaces using... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4089055