Elastic store circuit with vernier clock delay

Details Elastic store circuit with vernier clock delay Elastic store circuit with vernier clock delay

1999-10-20

2003-09-30

Lee, Thomas (Department: 2185)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

Using delay

C713S400000, C713S600000, C710S052000

Reexamination Certificate

active

06629251

ABSTRACT:

BACKGROUND AND SUMMARY OF THE INVENTION
This invention is generally related to integrated circuit (IC) signal timing circuitry and, more particularly, to a method of delaying signals through an elastic store for times of less than a clock cycle, through precise control of the clocking signals.
An elastic store is a circuit often used in a receiver to acquire asynchronous input data, or to collect data from sources with unpredictable transmission delays. The elastic store can also be used to combine multiplexed data sources. That is, the elastic store receives data at uncertain clock rates and converts it to the receiver clock rate. Conventionally, the elastic store accepts data at a write (WR) clock rate, and supplies it at the read (RD) clock rate. A commutator system is used to create delay by adjusting the number of clock cycles between when data is written, and when it is read.
Conventional elastic store circuits provide a delay of at least one clock cycle. These circuits are useful if large delays are required between the input and output data. However, problems arise in using elastic stores to create a delay of less than a clock cycle. Neither are conventional elastic stores useful if a delay equal to a non-integer value of a clock cycle is required, for example, a delay of 1.5 clock cycles. It is possible to add delay circuitry to the input or output data lines of the elastic store to achieve delays that are not an integer value of a clock cycle. However, keeping such delay circuitry synchronously aligned with the WR and RD clocks of the elastic store is a problem. Further, such delay circuitry is not readily available for high speed waveforms.
In co-pending patent application Ser. No. 09/420,976, entitled “ELASTIC STORE CIRCUIT WITH STATIC PHASE OFFSET,” filed on Oct. 20, 1999, Anderson et al. disclose a system of controlled delay in an elastic store device with the introduction of a phase offset to the read clock, which results in elastic store delays of much less than a read or write clock cycle.
It would be advantageous if an elastic store could delay data for periods of time that are less than the WR and RD clock cycles to provide precise control over the timing of signals.
It would be advantageous if delays of less than a WR/RD clock cycle could be made programmable and repeatable.
It would be advantageous if non-integer clock cycle delays could be maintained in a synchronous relationship to the WR and RD clocks.
It would be advantageous if an elastic store had the capacity to delay data signals in increments of time greater than a WR/RD clock cycle, simultaneously with the capacity to make adjustments that are in increments smaller than the period of a WR/RD clock.
Accordingly, an elastic store is provided with programmable delay. The elastic store comprises a vernier circuit having an input to accept the reference clock. The vernier circuit also accepts a digital control signal, to provide the reference clock with a first delay at its output.
The elastic store also includes a first in/first out (FIFO) circuit: The FIFO has a first input to receive data input, and a second input to accept a write (WR) clock that is synchronous to the reference clock. The FIFO has a third input to accept a read (RD) clock which is synchronous to the delayed reference clock. Therefore, the FIFO reads data input at the rate of the delayed RD clock. Because the delay is accomplished with the clocks, instead of in the data lines, fine delays of less than one RD clock cycle can be accomplished.
A first clock synthesizer unit (CSU) receives the delayed reference clock from the vernier circuit, and supplies the RD clock to the FIFO. A second CSU receives the reference clock and provides the WR clock to the FIFO.
In one aspect of the invention, a multiplexer (MUX) circuit is provided which accepts parallel data input signals. The MUX also receives the WR clock from the second CSU, and the parallel data lines are combined into a serial data stream at the WR clock rate.
A method for precisely controlling the delay of input data in a FIFO data transfer is also provided comprising the steps of:
a) generating a reference clock;
b) generating a WR clock, synchronous to the reference clock;
c) delaying the reference clock to create a delayed reference clock;
d) generating a RD clock, synchronous to the delayed reference clock;
e) writing input data at the WR clock rate; and
f) reading the input data at the RD clock rate, whereby an elastic store with a precise delay is created.


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