Static information storage and retrieval – Systems using particular element – Flip-flop
Reexamination Certificate
2011-01-11
2011-01-11
Hoang, Huan (Department: 2827)
Static information storage and retrieval
Systems using particular element
Flip-flop
C365S156000, C365S226000
Reexamination Certificate
active
07869263
ABSTRACT:
An elastic power header device and methods of operation are provided to improve the read margin of static random access memory (SRAM) cells by increasing read stability, reducing read disturbance and improving the Signal to Noise Margin (SNM) figure of merit. For example, various implementations of an elastic power header device are utilized as programmable resistances to permit the power supply lines to reach a maximum voltage. Allowing the power supply lines to reach the reference voltage allows more flexibility in read margin and read stability. Furthermore, this additional flexibility can be controlled by means for adjusting a voltage. This adjustment voltage can fine-tune the programmable resistances so that the read margin can be more conveniently controlled.
REFERENCES:
patent: 4982365 (1991-01-01), Ohtani et al.
patent: 5870331 (1999-02-01), Hwang et al.
patent: 6147898 (2000-11-01), Yamada
patent: 6635936 (2003-10-01), Wuu et al.
patent: 6771095 (2004-08-01), Dunlea et al.
patent: 6781870 (2004-08-01), Kushida
patent: 7092280 (2006-08-01), Joshi
patent: 7495948 (2009-02-01), Suzuki et al.
patent: 7502275 (2009-03-01), Nii et al.
patent: 2004/0217448 (2004-11-01), Kumagai et al.
patent: 2006/0268626 (2006-11-01), Hamzaoglu et al.
patent: 2007/0013428 (2007-01-01), Vadi et al.
patent: 2007/0030741 (2007-02-01), Nii et al.
patent: 2007018780 (2007-02-01), None
V. Degalahal et al, “Soft Errors Issues in Low-Power Caches,” IEEE Transactions on VLSI Systems, vol. 13, No. 10, Oct. 2005, pp. 1157-1166.
V. Degalahal et al, “Analyzing Soft Errors in Leakage Optimized SRAM Design,” Proceedings of the 16th International Conference on VLSI Design, Jan. 4-8, 2003, pp. 1-7.
Y. Lih et al, “A Leakage Current Replica Keeper for Dynamic Circuits,” IEEE Journal of Solid-State Circuits, vol. 42, No. 1, Jan. 2007, pp. 48-55.
M. Yamaoka et al, “90-nm Process-Variation Adaptive Embedded SRAM Modules with Power-Line-Floating Write Technique,” IEEE Journal of Solid-State Circuits, vol. 41, No. 3, Mar. 2006, pp. 705-711.
K. Zhang et al, “A 3-GHz 7-Mb SRAM in 65-nm CMOS Technology with Integrated Column-Based Dynamic Power Supply,” IEEE Journal of Solid-State Circuits, vol. 41, No. 1, Jan. 2006, pp. 146-151.
N. Mokhoff, “Digital Designer's Plight Debated at ISSCC,” http://www.eetimes.com/showArticle.jhtml? articleID=179101341, Feb. 7, 2006, pp. 1-2.
E. Seevinck et al, “Static-Noise Margin Analysis of MOS SRAM Cells,” IEEE Journal of Solid-State Circuits, vol. SC-22, No. 5, Oct. 1987, pp. 748-754.
B. Calhoun and A. Chandrakasan, “Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm CMOS,” Proceedings of ESSCIRC, Sep. 2005, pp. 363-366.
International Search Report for International Application No. PCT/US2006024680, dated Jan. 12, 2006, pp. 1-3.
M. Horstmann et al, “Advanced Transistor Structures for High Performance Microprocessors,” International Conference on Integrated Circuit Design and Technology, May 17-20, 2004, pp. 65-71.
H. S. Yang et al, “Dual Stress Liner for High Performance sub-45nm Gate Length SOI CMOS Manufacturing,” IEDM Technical Digest, Dec. 13-15, 2004, pp. 1075-1077.
PCT International Preliminary Report on Patentability dated Aug. 13, 2009, 7 pages.
European Search Report for European Application No. 08728581.3-1233 dated Mar. 4, 2010, 7 pages.
Balasubramanian Shyam
Bhatia Ajay
Fung Daniel
Lih Yolin
Liu Jun
Hoang Huan
Oracle America Inc.
Osha • Liang LLP
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