Elastic buffer with bidirectional phase detector

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

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Details

370102, 370108, H04L 700, H04L 2536, H04L 2540

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active

054286492

ABSTRACT:
An elastic buffer utilizes a circular buffer for receiving successive symbols over a communications link. The transmission clock of the received symbols and internal clock of the node on which the elastic buffer is located are independent. The transmission clock is used to load the successive symbols received over the transmission link into the circular buffer. The internal clock controls reading of the successive symbols from the circular buffer. A phase comparator operating on the transmission and internal clocks periodically generates an input side skip signal when the transmission clock overtakes the phase of the internal clock and an output side skip signal when the internal clock overtakes the phase of the external clock. An idle symbol detector monitors the successive symbols generates an idle indication when an idle symbol occurs. Responsive to concurrence of an input side skip signal and an idle indication, loading of an idle symbol from successive symbols into the circular buffer is omitted. Responsive to occurrence of an output side skip signal, the reading of successive symbols from the circular buffer is delayed for an internal clock period.

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"IEEE Standard for Scalable Coherent Interface (SCI)", Institute of Electrical and Electronics Engineers, Inc., IEEE Std. 1596-1992, New York, N.Y., Aug. 2, 1993, pp. 1-83.

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