Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Patent
1997-07-14
2000-07-11
Chin, Stephen
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
375371, 375354, 710 56, H04L 700
Patent
active
060884126
ABSTRACT:
The present invention comprises an elastic buffer to interface digital systems and eliminate sample slippage. The system of the present invention includes a FIFO buffer, a signal classifier, and a FIFO manager. The FIFO buffer receives and stores a plurality of samples as they are received from a transmitting digital system. The plurality of samples comprise a received digital signal and are stored on a first in first out basis. The signal classifier is coupled to the FIFO buffer. The signal classifier is adapted to identify non-essential samples among the plurality of samples stored in the FIFO buffer. The FIFO manager is coupled to the FIFO buffer and the signal classifier. The FIFO manager is adapted to remove the non-essential samples identified by the signal classifier, or, insert additional non-essential samples into the plurality of samples stored within the FIFO buffer. When the FIFO buffer is in an underrunning condition, the additional non-essential samples are inserted. When the FIFO buffer is in an overrunnng condition, the non-essential samples are removed. Thus, non-essential samples are removed or inserted into the FIFO buffer such that the plurality of samples comprising the digital signals are output to a receiver at the receiver's sample rate, eliminating sample slippage.
REFERENCES:
patent: 5602882 (1997-02-01), Co et al.
patent: 5771356 (1998-06-01), Leger et al.
patent: 5796796 (1998-08-01), Wang
patent: 5864714 (1999-01-01), Tal et al.
Chin Stephen
Liu Shuwang
VLSI Technology Inc.
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