Apparatus for reducing jitter in a desynchronizer

Details Apparatus for reducing jitter in a desynchronizer Apparatus for reducing jitter in a desynchronizer

1998-04-13

2000-07-11

Pham, Chi H.

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

370506, 370516, H04L 700, H04L 2500, H04L 2540

Patent

active

060884134

ABSTRACT:
An apparatus, to be used in a desynchronizer, for minimizing the output jitter of the desynchronizer. The desynchronizer is assumed to include a bit buffer for staging data that is to be output. The desynchronizer is also assumed to include a means for decoding the input signal to determine how justification opportunities in the input signal are used and therefore what justification bits must be leaked by the desynchronizer. The apparatus and method of the present invention uses the information about the incoming justification bits or incoming justification bytes and the state of the buffer to determine the longest possible time to wait before issuing a command to momentarily speed up or delay outputting the next data unit from the bit buffer. This speeding up or delay is caused by sending a clock signal to the bit buffer that is shifted in phase by a small amount, thereby spreading out the effect of an incoming positive or negative justification bit or byte over many periods of the output clock of the desynchronizer.

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