Efficient variably-channelized SONET multiplexer and payload...

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses

Reexamination Certificate

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Details

C370S907000, C370S916000

Reexamination Certificate

active

07000136

ABSTRACT:
The present invention provides a multiplexed payload system for processing data organized in any interleaved framing structure, preferably SONET. Along a receive path, the system consists of an input shift register, an input multi-stream merge network, a time-sliced processing unit, and a context memory. Similarly, along a transmit path, the system consists of an output shift register, an output multi-stream merge network, a time-sliced processing unit, and a context memory. The transmit path functions in an identical manner to the receive path but in the reverse direction. The multi-stream merge network, in either direction, converts between spatially separated input data streams of various configurable widths and time-division-multiplexed streams of constant width. The input shift register and the output shift register serve to accept a serial stream of bytes from the data receiver and convert them to a parallel stream of bytes presented to the input multi-stream merge network, or to accept a parallel stream of bytes from the output multi-stream merge network and convert them to a serial stream of bytes to the data transmitter, respectively. The context memory stores the processing contexts for sub-rate payload streams derived from the serial stream of bytes. A separate context memory location is assigned to each sub-rate payload stream that is received or transmitted. The time-sliced processing unit retrieves processing contexts from the context memory in a fixed sequence and uses the processing contexts to process data presented by the input multi-stream merge network, or generate data presented to the output multi-stream merge network.

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U.S. Appl. No. 09/812,821, filed Mar. 2001, Alexander et al.

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