Efficient parallel cyclic redundancy check calculation using...

Details Efficient parallel cyclic redundancy check calculation using... Efficient parallel cyclic redundancy check calculation using...

2006-08-15

2009-12-01

Chase, Shelly A (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C708S507000

Reexamination Certificate

active

07627802

ABSTRACT:
A system and method for cyclic redundancy checks (CRC) having a CRC polynomial of width (W) for use in a digital signal processing system is disclosed. The system includes receiving a message ({right arrow over (m)}) and decomposing that message ({right arrow over (m)}) into a series of smaller blocks ({right arrow over (b)}i). Each block ({right arrow over (b)}i) is of size (M) and is related to a unit vector ({right arrow over (e)}i). A summation operation on the blocks ({right arrow over (b)}i) given by CRC({right arrow over (b)})=Σbi·CRC({right arrow over (e)}i) is performed. Each CRC of the unit vectors (CRC({right arrow over (e)}i)) is stored in a lookup table. The lookup table is tagged by the “one” bits of the message block. An exclusive OR (XOR) operation is performed on each tagged row of the lookup table to calculate the CRC of the message.

REFERENCES:
patent: 5619516 (1997-04-01), Li et al.
patent: 6029186 (2000-02-01), DesJardins et al.
patent: 6904558 (2005-06-01), Cavanna et al.

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