Efficient method for fabricating P-wells and N-wells

Details Efficient method for fabricating P-wells and N-wells Efficient method for fabricating P-wells and N-wells

1997-06-20

1999-07-20

Brown, Peter Toby

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438232, 438298, 438420, 438526, H01L 218238

Patent

active

059267046

ABSTRACT:
A method forms, in a CMOS semiconductor substrate, P- and N-wells having independently optimized field regions and active regions. In one embodiment, P- and N-wells are formed by (i) creating in successive steps the field regions of the P- and N-wells; (ii) creating an oxide layer over the field regions, (iii) creating in successive steps the active regions. The method achieves the P- and N-wells without increasing the number of photoresist masking steps. In addition, optical alignment targets (OATs) are optionally formed simultaneously with these P- and N-wells without increasing the total number of process steps.

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patent: 5384279 (1995-01-01), Stolmeijer et al.
patent: 5427964 (1995-06-01), Kaneshiro et al.
patent: 5679588 (1997-10-01), Choi et al.

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