Efficient fabrication process for dual well type structures

Details Efficient fabrication process for dual well type structures Efficient fabrication process for dual well type structures

1999-05-14

2001-07-31

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S276000, C438S119000, C438S217000, C438S203000, C438S200000

Reexamination Certificate

active

06268250

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of integrated circuit fabrication, and more specifically to a fabrication process for use when two well types are required on a single integrated circuit.
2. Description of the Related Art
It is often necessary or desirable to fabricate both n-type and p-type devices on a single substrate. In order to fabricate both types of devices in a single substrate, typically a large area of a substrate of one type is doped to the other type. This large area is referred to as a “well.” For example,
FIG. 1
illustrates a portion
100
of an integrated circuit on a p-type substrate
110
. The substrate
110
has an n-well (a well formed of n-type material)
120
formed therein. Inside the n-cell
120
are a p-type source
141
and drain
142
on either side of a gate stack
150
, which is formed of a gate dielectric
151
, a gate electrode
158
and an insulating cap
159
. Together, the gate stack
150
and the source and drain
141
,
142
form a p-type field effect transistor
160
. Field oxide regions
130
isolate the transistor
160
from other devices on the substrate
110
.
Conventional wells are formed by implanting dopants at the well locations and then diffusing them (usually through a thermal process) to the desired depth. Such wells are also referred to as diffusion wells for this reason. One drawback associated with diffusion wells is that the diffusion occurs laterally as well as vertically, e.g. the diffusion well gets wider as it gets deeper. A second drawback associated with diffusion wells is that relatively large spaces between the edges of the wells and device active areas is required.
A second type of well, referred to as a retrograde well, attempts to overcome the lateral spreading problem by implanting high energy dopants to the desired depth so that thermal diffusion is not necessary. Retrograde wells require less space between the edges of the well and device active areas than required by diffusion wells. Retrograde wells are therefore desirable for high density applications.
In certain applications, it makes sense to use both well types on a single integrated circuit. For example, in flash memory applications, which contain a low voltage peripheral circuit portion and a high-voltage peripheral circuit portion, it is desirable to have the low voltage peripheral circuit portion implemented in retrograde wells and the high voltage peripheral circuit portion implemented in conventional diffusion wells. This type of structure is discussed in Watanabe et al., “Novel 0.44 &mgr;m
2
Ti-Salicide STI Technology for High Density NOR Flash Memories and High Performance Embedded Application,” IEDM 98-975 (IEEE 1998). Another example of a device using both diffusion and retrograde wells on a single integrated circuit is described in U.S. Pat. No. 5,428,239, to Okamura et al.
Although these references disclose use of dual well type structures, they do not disclose an efficient method for fabrication such structures. Thus, integrated circuit manufacturers are faced with choosing between the benefits of using a dual well type structure one hand and the less complicated fabrication processes required for single well type structures on the other hand.
What is needed is an efficient method for fabricating a dual well type structure.
SUMMARY OF THE INVENTION
The invention overcomes to a great extent the aforementioned problems by providing an efficient method for fabricating structures with two types of wells which uses the same number of masks as used in single well type structure fabrication. In a preferred embodiment, the current invention allows low voltage and high voltage n-channel transistors and low voltage and high voltage p-channel transistors to be formed in a single substrate. One mask is used for forming a diffusion well, a second mask for both forming a retrograde well and doping the retrograde well to achieve an intermediate threshold voltage in that well, and a third mask for both differentiating the gate oxides for the low voltage devices and doping the areas of the substrate corresponding to the low voltage devices to achieve the final threshold voltages.


REFERENCES:
patent: 5428239 (1995-06-01), Okumura et al.
patent: 5726488 (1998-03-01), Watanabe et al.
patent: 5753956 (1998-05-01), Honeycutt et al.
patent: 5773863 (1998-06-01), Burr et al.
patent: 5814866 (1998-09-01), Borland
patent: 5821153 (1998-10-01), Tsai et al.
patent: 5830795 (1998-11-01), Mehta et al.
patent: 5851863 (1998-12-01), Fujii et al.
patent: 5851864 (1998-12-01), Ito et al.
patent: 5960274 (1999-09-01), Mehta
patent: 6005797 (1999-12-01), Porter et al.
patent: 6090652 (2000-07-01), Kim
H. Watanabe et al. “NOVEL 0.44 &mgr;m2Ti-Salicide STI Cell Technology for High-Density NOR Flash Memories and High Performance Embedded Application,” IEEE 1998, 5 pages.

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