Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-12-28
2002-04-16
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C700S121000, C700S096000, C700S109000
Reexamination Certificate
active
06374398
ABSTRACT:
TECHNICAL FIELD
The present invention relates to integrated circuit design and fabrication. More specifically, the present invention pertains to a method and system for calculating the number of integrated circuit dies per wafer and the stepper shot count for different wafer sizes using lookup tables.
BACKGROUND ART
Integrated circuit dies are fabricated en masse on silicon wafers using well-known techniques such as photolithography. Using these techniques, a pattern that defines the size and shape of the components and interconnects within a given layer of the die is applied to the wafer. The pattern applied to the wafer is laid out in an array, or matrix, of reticle images. A wafer stepper holds the pattern over a wafer and projects the pattern image of the reticle onto the wafer. The area on the wafer upon which the image is projected is defined as a stepper shot. A multitude of interconnecting layers, one formed on top of another, are essentially built up on the integrated circuit dies using several passes through the stepper.
The gross number of dies that can be produced from a single wafer is, as would be expected, dependent on the size and shape of the individual dies. The number of stepper shots is dependent on the number of die images that can be placed in the printable field of the reticle, which in turn is dependent on the size and shape of the individual dies. Therefore, the number of stepper shots is also dependent on the size and shape of the individual dies.
It may not always be desirable to maximize the number of dies produced per wafer. If the fabrication facility wafer steppers are not being used to capacity, then it generally is appropriate to adjust die size and shape to maximize the gross number of dies per wafer. On the other hand, if the fabrication facility is capacity limited by its wafer steppers, it may be more important to minimize the stepper shot count. When the fabrication facility is fully loaded, it may be beneficial to accept slightly fewer dies per wafer if the number of stepper shots is reduced as a result, thereby allowing more wafers to be processed during a given timeframe and consequently producing a greater number of total dies.
However, the prior art is problematic because decisions may be made in the design phase without fully considering the effect on the fabrication phase. In the prior art, the design phase and the fabrication phase of the integrated circuit die production process may be separate and independent from each other. In the design phase, the integrated circuit die must be designed to have a surface area large enough to accommodate the microcircuitry that will be included in the integrated circuit. The designer will typically choose dimensions that provide a size and shape that provide the required surface area, but may pay lesser regard to selecting dimensions that, along with providing the required surface area, also maximize the gross number of dies per wafer.
In some instances in the prior art, an effort may be made to coordinate the design phase with the fabrication phase. As might be expected, this coordination may not always take place. However, even in those cases where a more formal process is used to coordinate design and fabrication, the prior art is still problematic because the dimensions of the die are often chosen with the goal of maximizing the number of dies per wafer, without considering the number of stepper shots needed to produce the dies. As described above, it is not always desirable to maximize the number of dies produced per wafer.
In order to facilitate coordination between the design and fabrication processes, one solution is a method and system whereby a designer inputs proposed dimensions for a die and receives as output the results of a calculation of number of dies per wafer and stepper shot count. The designer can iterate using different dimensions until desirable values of the number of dies per wafer and stepper shot count are obtained. Additional information regarding this solution is provided in the copending patent application filed concurrently herewith, assigned to the assignee of the present invention, entitled “Method And System for Varying Die Shape to Increase Wafer Productivity,” by Wesley R. Erck, Michael R. Magee, and Michael D. Beer, with Ser. No. 09/473,384, hereby incorporated by reference.
In one implementation of the solution described by this reference, lookup tables are used to compute the die count and the stepper shot count. These lookup tables are a function of the different parameters that can affect the number of die per wafer and the stepper shot count, such as the wafer size and production method (e.g., ceramic package, plastic package, narrow scribe, stepper type, and the like). Thus, a multiplicity of different lookup tables may be needed in order to account for the different parameters that can affect the results. For example, a die count lookup table and a stepper shot count lookup table are needed for each combination of the different parameters that can affect the results.
Furthermore, when a new parameter affecting the number of die per wafer or the stepper shot count is introduced, or when an existing parameter is changed to a new value, then a new lookup table needs to be generated, consuming time, computer processing resources, and file space. For example, if a new production method is implemented, new lookup tables need to be generated for each wafer size, etc.
One approach for reducing the number of lookup tables is provided in the copending patent application filed concurrently herewith, assigned to the assignee of the present invention, entitled “Computation of Die-Per-Wafer Considering Production Technology and Wafer Size,” by Michael R. Magee, Michael D. Beer, and Wesley R. Erck, with Ser. No. 09/473,525, hereby incorporated by reference. This reference describes a method in which a “die element size” is used as the basis for the information in the lookup tables. The die element size is a function of scribe lane width, guard ring width, input/output pad area, and length and width of the die. The die element size thus accounts for the different production parameters, and therefore a die count lookup table and a stepper shot count lookup table are needed only for each wafer size. Consequently, the number of required lookup tables is reduced.
However, the lookup tables for each wafer size contain a large amount of data. Thus, each lookup table can take a relatively long period of time to generate, consuming a significant portion of a computer system's processing resources for an extended period of time. In addition, a large lookup table can also be somewhat cumbersome to work with, and so delays may be incurred when downloading a lookup table, reading it, and looking up and retrieving the information needed.
Accordingly, what is needed is a method and/or system that can facilitate coordination between the design and fabrication phases of integrated circuit die production and also can reduce the impact on computational resources, in particular with regard to the resources needed to generate, store and use lookup tables used to calculate die per wafer and stepper shot count as a function of die element size. The present invention provides a novel solution to the above needs.
These and other objects and advantages of the present invention will become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.
DISCLOSURE OF THE INVENTION
The present invention provides a method and system thereof that can facilitate coordination between the design and fabrication phases of integrated circuit die production and can reduce the impact on computational resources, in particular with regard to the resources needed to generate, store and use lookup tables used to calculate die per wafer and stepper shot count as a function of die element size.
The present embodiment of the present invention pertains to a method and system thereof for co
Beer Michael D.
Erck Wesley R.
Magee Michael R.
Kik Phallaka
Smith Matthew
VLSI Technology Inc.
Wagner , Murabito & Hao LLP
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