Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1999-06-21
2003-04-01
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C324S765010
Reexamination Certificate
active
06543015
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
This invention relates to memory testing and in particular the compression of test data to provide efficiency in testing a plurality of memory sections and data I/O.
2. Description of Related Art
The testing of integrated circuits has many challenges for reducing test time. The same data can be written to a number of memory cells at the same time and then read out to be compared with the written data to reduce the number of addresses used during testing. Also memory chips can have more than one output terminal. Testing can be constrained by the space needed to support a number of output pins on a test board.
In U.S. Pat. No. 5,896,333 (Nakashima et al.) is described a memory test using a timer that is controlled to be shorter in length than the time allowed during normal memory operations. In U.S. Pat. No. 5,892,721 (Kim) describes a parallel test circuit for a memory where a main amplifier compares and amplifies two bit data capable of testing a 2n number of data with an n number of main amplifiers. In K. Furutani et al., “A Board Level Parallel Test and Short Circuit Failure Repair Circuit for High Density, Low Power DRAMS”, Symposium on VLSI Circuits Digest of Technical Papers, pp 70-71, 1996; a board level parallel test circuit is proposed as a means to be able to perform such tests as data retention time and cope with the increasing density of DRAMs. In John Wu et al., “An SDRAM Interface for Simplified “At-Speed” Testing of the SLDRAM Internal Array”, Proceedings, International Workshop on Memory Technology, design and Testing, pp 38-44, 1998; the testing and characterization of an SDRAM array is discussed without the cost of using high speed testers for the entire test and characterization program.
Data compression provides a means by which the data of a plurality of I/O can be compressed to one output to provide a single pass/fail result. This can be extremely useful when testing a plurality of memory chips where the space to monitor each output is limited.
SUMMARY OF THE INVENTION
In this invention an address compression circuit and an I/O compression circuit are combined. The memory address compression result is connected to a data output circuit and several data output circuits are compressed in an I/O compression circuit. This produces a single output containing the combined test results of a plurality of memory addresses and a plurality of I/O circuits. There are three states of the combined address compression and the I/O compression; a logical zero that defines all test results are good, a logical one and a high impedance state (HiZ) that indicate that one or more addresses and/or I/O circuits are bad.
The ability to produce a combined result with the two compression circuits is a result of the two compression circuits having different truth tables. The address compression circuit indicates a failure with a logical one, and the I/O compression circuit controls the high and low impedance of the output. The output of the combined address and I/O compression circuits produce a logical zero to indicate all data that is compressed is correct and all other output states, which include HiZ and a logical one, indicate that a least one compressed piece of data is incorrect.
If the combined compression circuits are used at the wafer test, failing chips are sent back for diagnostics and repair. At the package level, a detected failure is not repairable, and the part exhibiting a failure is discarded. The use of the I/O compression allows more chips to be tested because there is more space available as a result of fewer support circuits needed to accommodate a fewer number of I/O output pins having test data.
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Farutani et al., “A Board Level Parallel Test and Short Circuit Failure Repair Circuit for High-Density, Low-Power DRAM's”, Symposium on VLSI Circuits Digest of Technical Papers, pp. 70-71, 1996.
Wu et al., “An SDRAM Interface for Simplified “At Speed” Testing of the SLDRAM Internal Array”.
Proceedings, International Workshop on Memory Technology, Design and Testing, pp. 38-44, 1998.
Wang Gyh-Bin
Yuan Der-Min
Ackerman Stephen B.
De'cady Albert
Etron Technology Inc.
Lamarre Guy
Saile George O.
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