Efficiency improved DRAM row redundancy circuit

Details Efficiency improved DRAM row redundancy circuit Efficiency improved DRAM row redundancy circuit

1991-05-16

1993-10-26

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Bad bit

36518907, 36523006, 371 101, G11C 1140

Patent

active

052572285

ABSTRACT:
A redundancy scheme for a memory is disclosed which allows defect correction, particularly, word line to word line short correction through the use of a minimal number of redundant lines. The scheme makes use of some logical function of the non-matching address bits of two word lines between which a word line to word line short exists. The logical function can comprise the exclusive OR, or some function of the exclusive OR (i.e. exclusive NOR of the non-matching address bits of two word lines between which a word line to word line short exists.

REFERENCES:
patent: 4471472 (1984-07-01), Young
patent: 4494220 (1985-02-01), Dumbri et al.
patent: 4538247 (1985-08-01), Venkateswaran
patent: 4737935 (1988-04-01), Wawersig et al.

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