Effective load length increase by topography

Details Effective load length increase by topography Effective load length increase by topography

1996-04-19

1998-05-26

Monin, Donald

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257538, 257904, H01L 2702, H01L 2976

Patent

active

057570531

ABSTRACT:
A device and a method of manufacture of a semiconductor device on a semiconductor substrate including an SRAM cell with a resistor comprises forming a first polycrystalline silicon containing layer on the semiconductor substrate, patterning and etching the first polycrystalline silicon containing layer to form steps on either side thereof, forming a dielectric layer over the first polycrystalline silicon containing layer with the steps on either side of the first polycrystalline silicon containing layer, forming a blanket of a second polycrystalline silicon containing layer extending over the interpolysilicon layer, and ion implanting the second polycrystalline silicon containing layer in a blanket implant of a light dose of dopant including ion implanting resistive regions with far higher resistivity in the regions over the steps.

REFERENCES:
patent: 5087956 (1992-02-01), Ikeda et al.
patent: 5268325 (1993-12-01), Spinner, III et al.
patent: 5543652 (1996-08-01), Ikeda et al.
Ohzone et al., "A 2K.times.8-Bit Static MOS RAM with a New Memory Cell Structure", IEEE Journ. of SS Cir., vol. SC-15, No. 2, Apr. 1980 pp. 201-205.

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