Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-01-04
2001-04-24
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S687000, C438S685000, C438S627000, C438S640000, C438S648000, C438S643000
Reexamination Certificate
active
06221758
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor devices and more particularly to diffusion barriers for conductors.
2. Description of Related Art
U.S. Pat. No. 5,714,418 of Bai et al. for “Diffusion Barrier for Electrical Interconnects in an Integrated Circuit” discloses a bi-layer barrier for a copper interconnect using titanium/tantalum (Ti/Ta) or tantalum nitride (TaN).
U.S. Pat. No. 5,668,054 of Sun et al. for “Process for Fabricating Tantalum Nitride Diffusion Barrier for Copper Metallization” shows a tantalum nitride (TaN) diffusing barrier for a copper interconnect.
U.S. Pat. No. 4,931,410 of Tokunaga et al. for “Process for Producing Semiconductor Integrated Circuit Device Having Copper Interconnections and/or Wirings, and Device Produced” shows a copper (Cu) wire interconnect process.
U.S. Pat. No. 5,674,787 of Zhoa et al. for “Selective Electroless Copper Deposited Interconnect Plugs for ULSI Applications” mentions a tantalum barrier for a copper interconnect. See col. 5.
SUMMARY OF THE INVENTION
This invention provides a Ta barrier layer and filling/stuffing process for a Cu interconnect process.
Before deposition of a copper interconnect conductor tantalum (Ta) is deposited. Next the initial tantalum film is filled, i.e. stuffed with an oxide and/or a nitride to form an enhanced tantalum (Ta) barrier layer by exposure to room temperature atmospheric air or exposure to a nitrous oxide (N
2
O) gas in a plasma to improve barrier properties. This improves the barrier properties of the tantalum (Ta) by the oxygen (O
2
) gas or N
2
O to fill or stuff the grain boundaries of the tantalum metal film. The tantalum film can be filled with oxygen and/or nitrogen preferably at about 600° C. or in a plasma at a lower temperature of about 400° C. The filled tantalum film can be formed by exposure to a nitrous oxide (N
2
O) gas in a plasma at a temperature of about 400° C. Next, the filled tantalum film is coated with a redeposited tantalum layer. This simultaneously avoids degrading of the adhesion between the tantalum (Ta) the copper (Cu) layers which are added on top of the refilled tantalum layer.
In accordance with this invention, a method is provided for forming a semiconductor device in which an electrically conductive substrate is covered with a dielectric layer by the following steps. Form a trench in the dielectric layer reaching down to expose a portion of the substrate, the trench having walls. The trench is precleaned prior to forming the tantalum film. Form a tantalum film superjacent to the dielectric layer including the walls and covering the portion of the substrate. Fill the tantalum film by oxidizing to form at least one of tantalum oxide and tantalum nitride forming a filled tantalum film. After filling the tantalum film a redeposited tantalum layer is formed superjacent to the filled tantalum film. Form a copper seed film superjacent to the redeposited tantalum film. Plate the device filling the trench with a plated bulk copper layer superjacent to the copper seed film. Planarize the device to expose the top surface of the dielectric layer, removing surplus portions of the filled tantalum film, the copper seed film, and the bulk copper layer. Preferably, the filled tantalum film is formed by exposing the tantalum to air under STP atmospheric conditions; or the filled tantalum film is formed by exposure to a nitrous oxide (N
2
O) gas in a plasma at a temperature of about 600° C.
In accordance with another aspect of this invention, a semiconductor device has an electrically conductive substrate is covered with a dielectric layer with a trench formed therein reaching down to expose a portion of the substrate. The trench was precleaned prior to forming a tantalum film which is over the dielectric layer including the walls and covering the portion of the substrate. The tantalum film has grain boundaries filled with at least one of tantalum oxide and tantalum nitride forming a filled tantalum film. There are a redeposited tantalum layer over the filled tantalum film and a copper seed film over the redeposited tantalum film. The trench is filled with a plated bulk copper layer over the copper seed film, and the device is planarized to expose the top surface of the dielectric layer, after removal of surplus portions of the filled tantalum film, the copper seed film, and the bulk copper layer. Preferably, the filled tantalum film was exposed to air under STP atmospheric conditions or to a nitrous oxide (N
2
O) gas in a plasma at a temperature of about 600° C.
REFERENCES:
patent: 4931410 (1990-06-01), Tokunaga et al.
patent: 5326404 (1994-07-01), Sato
patent: 5668054 (1997-09-01), Sun et al.
patent: 5674787 (1997-10-01), Zhao et al.
patent: 5714418 (1998-02-01), Bai et al.
patent: 5893752 (1999-04-01), Zhang et al.
patent: 6057231 (2000-05-01), Givens et al.
Liu Chung-Shi
Shue Shau-Lin
Yu Chen-Hua
Ackerman Stephen B.
Bowers Charles
Jones II Graham S.
Nguyen Thanh
Saile George O.
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