Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-06-29
2004-10-12
Thomas, Tom (Department: 2815)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S211000, C438S257000, C438S622000
Reexamination Certificate
active
06803268
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor device, and more particularly to a semiconductor device including an electrically erasable programmable read only memory having a two-gate structure of a floating gate and a control gate deposited on the floating gate.
2. Description of the Related Art
An electrically erasable programmable read only memory (hereinafter, referred to simply as “EEPROM”) generally includes, as a memory cell, MISFET memory transistor having a two-gate structure of a floating gate and a control gate formed on the floating gate. Data is written into or eliminated from the two-gate type EEPROM by introducing electric charges into or discharging electric charges from a floating gate.
For instance, data is written into the two-gate type EEPROM by introducing channel hot electrons, generated in drain regions, into a floating gate, whereas data is eliminated from EEPROM by introducing electrons into a source, for instance, by virtue of Fowler-Nordheim tunneling.
A conventional method of fabricating a two-gate type memory cell array is explained hereinbelow with reference to
FIGS. 1
,
2
and
3
A to
3
D, wherein
FIG. 1
is a plan view of a conventional two-gate type memory cell array,
FIG. 2
is a plan view illustrating the memory cell array being fabricated, and
FIGS. 3A
to
3
D are cross-sectional views of the memory cell array taken along the line III—III in
FIG. 1
, showing respective steps of a method of fabricating the memory cell array.
As illustrated in
FIG. 3A
, a p-type well
2
is formed in a p-type semiconductor substrate
1
in a region where a memory cell array is to be formed. Then, a plurality of field insulating films
3
is formed in the form of islands by selective oxidation. The field insulating films are not illustrated in
FIG. 3A
, but are insulated in FIG.
2
.
Then, a first gate insulating film
4
is formed all over the p-type well
2
, and a first polysilicon layer
5
a
is formed all over the first gate insulating film
4
for forming a floating gate. Then, impurities such as phosphorus (P) are doped into the first polysilicon layer
5
a
by thermal diffusion or ion-implantation to thereby lower a resistance of the first polysilicon layer
5
a
. Then, as illustrated in
FIG. 2
, the first polysilicon layer
5
a
is patterned into a plurality of layers
5
a
in parallel with each other so that the layers
5
a
extend perpendicularly to word lines which will be formed later, in order to define a width thereof in a direction of a channel width of a floating gate.
Then, a second gate insulating film
6
is formed all over the product, and a second polysilicon layer
7
a
is formed over the second gate insulating film
6
. Then, as illustrated in
FIG. 3A
, a patterned photoresist film
18
a
is formed on the second polysilicon layer
7
a
by photolithography and dry etching. The photoresist film
18
a
has a pattern for forming word lines.
Then, as illustrated in
FIG. 3B
, the second and first polysilicon layers
7
a
and
5
a
are patterned with the patterned photoresist film
18
a
being used as a mask, to thereby form control gates
7
and floating gates
5
. After removal of the photoresist film
18
a
, impurities such as arsenic (As) are ion-implanted into the product with the deposited gates
5
and
7
and the field insulating films
3
being used as a mask, to thereby form drain regions
8
a
and source regions
8
b.
Then, as illustrated in
FIG. 3C
, sidewall spacers
9
are formed around a sidewall of the deposited gates
5
and
7
of each of memory cells in order to cause CMOS transistors located outside memory cell array regions to have a LDD-structure. Thereafter, a first interlayer insulating film
10
is deposited all over the product. The first interlayer insulating film
10
is composed of boron phospho silicate glass (BPSG), and has a thickness in the range of 6000 to 8000 angstroms.
Then, there is formed a photoresist film
18
e
having a hole above the drain region
8
a
. Then, the first interlayer insulating film
10
is etched with the photoresist film
18
e
being used as a mask, to thereby form a contact hole
11
leading to the drain region
8
a.
After removal of the photoresist film
18
e
, aluminum alloy is deposited by sputtering by a thickness in the range of 4000 to 6000 angstroms. Then, the aluminum alloy is patterned by photolithography and dry etching to thereby form bit lines
12
extending perpendicularly to the word lines. Then, the product is entirely covered with a passivation film
16
composed of PSG and having a thickness of about 5000 angstroms. Thus, there is completed a memory cell array.
While the above-mentioned method is being carried out a region
3
a
(a hatched region in
FIG. 2
) which is sandwiched between the field insulating films
3
and will become a source region is exposed to etching twice, namely, when the first polysilicon layer
5
a
is patterned and when the second polysilicon layer
7
a
is patterned. When the first polysilicon layer
5
a
is patterned, the region
3
a
is covered merely with the thin first gate insulating film
4
after the first polysilicon layer
5
a
has been etched. Hence, the first gate insulating film
4
is first removed, and then, the p-type semiconductor substrate
1
is undesirably etched. In addition, when the second polysilicon layer
7
a
is patterned, the region
3
a
is covered merely with the thin second gate insulating film
6
after the second polysilicon layer
7
a
has been etched. Hence, the p-type semiconductor substrate
1
is undesirably further etched.
As a result, as illustrated in
FIG. 4
which is a cross-sectional view taken along the line IV—IV in
FIG. 1
, there is formed an undesirable recess
19
at a surface of the semiconductor substrate
1
. The undesirable recess
19
causes junction leakage therein, which poses a problem that data-writing and data-eliminating properties are deteriorated.
If a diffusion layer had a depth shallower than a depth of the recess
19
, there is formed a breakage in a source region at the recess
19
, since impurities are not ion-implanted into an inner sidewall of the recess
19
. This causes a reduction in a fabrication yield.
The above-mentioned problem can be solved by a semiconductor device structure as suggested in Japanese Unexamined Patent Publications Nos. 3-52267 and 3-126266, for instance. Hereinafter is explained the suggested structure with reference to
FIGS. 5
,
6
,
7
and
8
A to
8
D, wherein
FIG. 5
is a plan view of the suggested memory cell array,
FIG. 6
is a cross-sectional view taken along the line VI—VI in
FIG. 5
,
FIG. 7
is a cross-sectional view taken along the line VII—VII in
FIG. 5
, and
FIGS. 8A
to
8
D are cross-sectional views taken along the line VI—VI in
FIG. 5
, showing respective steps of a method of fabricating the suggested memory cell array.
The suggested memory cell array is characterized by that a plurality of the field insulating films
3
extend perpendicularly to the word lines
7
, and that the common source line
17
a
connecting the source regions
8
b
to each other in a direction in which the word lines
7
extend is formed to extend perpendicularly to the field insulating films
3
. Hereinafter is explained a method of fabricating the suggested memory cell array, with reference to
FIGS. 8A
to
8
D.
As illustrated in
FIG. 8A
, a p-type well
2
is formed in a p-type semiconductor substrate
1
by introducing p-type impurities into the semiconductor substrate
1
and thermally diffusing the p-type impurities and the semiconductor substrate
1
. Then, a plurality of field insulating films
3
are formed on a principal surface of the p-type well
2
by selective oxidation so that the field insulating films
3
extend in parallel with one another, but perpendicularly to word lines which will be formed later. The field insulating films
3
are not illustrated in
FIG. 8A
, but are illustrated in FIG.
5
.
Then, a first gate insulating film
4
and then a first polysilicon laye
Nagai Takaaki
Shinmori Masahiro
Brock II Paul E
Foley & Lardner LLP
NEC Electronics Corporation
Thomas Tom
LandOfFree
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