EEPROM memory cell with increased dielectric integrity

Details EEPROM memory cell with increased dielectric integrity EEPROM memory cell with increased dielectric integrity

1998-11-18

2003-02-11

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S263000, C438S594000

Reexamination Certificate

active

06518620

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention is directed to processes for fabricating MOS devices with ultrathin oxide layers, and particularly to EEPROM fabrication methods and structures.
Electrically Erasable Programmable Read Only Memories (EEPROMs) are nonvolatile memory devices that employ floating gates to store bits of data in individual cells. At each memory cell location, an ultrathin oxide layer called the “tunnel oxide” separates a floating gate from an underlying substrate. To program a memory cell, a voltage exceeding the normal operating voltage is applied to a control gate, which is capacitively coupled to the floating gate, to cause electrons to tunnel from the substrate through the tunnel oxide onto the floating gate in accordance with the well known Fowler-Nordheim principle. Electron tunneling occurs in the presence of a very high electric field applied to the tunnel oxide. Because the tunnel oxide is very thin and experiences such a high electric field, its dielectric integrity is an important design consideration.
An example of an early EEPROM memory cell is described in U.S. Pat. No. 4,203,158, in which a stacked-gate arrangement is employed to facilitate fabrication of a high density integrated circuit (IC) memory. Two layers of polycrystalline silicon (“polysilicon”) are used to fabricate the stacked gates. In each memory cell, a first-level polysilicon layer defines the floating gate and a second-level polysilicon layer defines the control gate. An equivalent circuit for one such memory cell is shown in
FIG. 1
herein, and is indicated generally by reference numeral
10
.
The memory cell
10
of
FIG. 1
communicates its stored bit of data to the outside world through a column bit line
12
. A series connection of a select transistor
14
and a floating-gate transistor
16
is provided between the bit line
12
and a voltage source or ground line
18
. The drain D of select transistor
14
is connected to the bit line
12
. The source S of transistor
14
is connected to the drain D of floating-gate transistor
16
. The source S of transistor
16
is connected to the source line
18
. Transistor
14
has its gate
20
controlled by a row select or “word” line
22
. Transistor
16
includes a floating gate
24
and a control gate
26
. A program select line
28
is connected to the control gate
26
.
To store a first binary logic level in the cell
10
, a high programming voltage (e.g., +20 volts) is applied to the word line
22
and to the program line
28
, while the bit line
12
and source line
18
are held at ground. By virtue of capacitive coupling, a sufficiently high voltage appears on the floating gate
24
to cause electrons to tunnel from the drain D of transistor
16
to the floating gate
24
, putting it in a negatively charged state. This causes transistor
16
to have a threshold voltage that is high enough to keep it off during a read operation. To store a second binary logic level in the memory cell
10
, the program line
28
is grounded while the high programming voltage is applied to the bit line
12
and to the word line
22
with the source line
18
left floating. This causes electrons to tunnel from the floating gate
24
to the drain D of transistor
16
, discharging the floating gate
24
and perhaps leaving it with a slight net positive charge. In this state, transistor
16
will have a threshold voltage such that it will be on during a read operation. As those skilled in the art will appreciate, reading is accomplished by applying a normal operating voltage (e.g., +5 volts) to the word line
22
and to the program line
28
, then detecting whether transistor
16
is on or off.
EEPROM memories can be manufactured as discrete integrated circuit devices or as components of more complex integrated circuit devices. When the EEPROM memory is included as a relatively small part of a more complex integrated circuit device, the allocation of chip area for each individual memory cell is not as critical as for high-density discrete EEPROMs. Therefore, when the EEPROM is part of a more complex integrated circuit device, it can be laid out using a single polysilicon layer rather than the stacked two-layer arrangement of the aforementioned patent. The slight additional area devoted to such a single-layer implementation does not appreciably effect the size of the integrated circuit device since its other circuitry occupies most of the chip area. The simplification of the fabrication process by resorting to single-layer polysilicon technology more than compensates for the slight additional chip area occupied by the EEPROM portion of the device.
A prior art layout for one EEPROM memory cell using single-layer polysilicon technology is illustrated in
FIG. 2
, wherein the memory cell is indicated generally by reference numeral
100
. A cross section through a portion of the memory cell
100
is illustrated in FIG.
3
. The cross section is taken through a floating-gate transistor
102
and a tunneling capacitor
104
.
FIG. 4
is an enlarged view of a portion of
FIG. 3
at one edge of the tunneling capacitor
104
.
With particular reference to
FIG. 3
, the device is fabricated on a P(−) substrate
106
. One of many, active areas of the device is shown defined within a thick field oxide
108
, typically formed by a conventional LOCOS (local oxidation of silicon) process. The active area is selectively doped with N-type impurities to create transistor regions and a capacitor plate. In particular, a relatively deep N-type region
110
defines a lower capacitor plate of the tunneling capacitor
104
. The junction depth of region
110
is typically 0.4 microns. An adjoining N-type region
112
at an intermediate depth (e.g., about 0.2 microns) defines the drain of floating-gate transistor
102
. Another intermediate depth N-type region
114
defines the source of floating-gate transistor
102
. Shallow N-type extensions
116
are formed by conventional lightly doped drain (“LDD”) processing, and define the channel
118
of transistor
102
therebetween. The floating-gate transistor
102
has a structure above the substrate
106
that includes a thin gate oxide
120
, a gate
122
and sidewall oxide spacers
124
. Similarly, the tunneling capacitor
104
has a structure above the substrate
106
that includes an ultrathin tunnel oxide
126
, an upper capacitor plate
128
, and sidewall oxide spacers
130
. Overlying and passivating the entire structure is a composite reflowed glass layer
132
, typically having an undoped SiO
2
lower portion and a doped SiO
2
upper portion (which are not separately delineated in the drawing).
Referring specifically to
FIG. 4
, the upper capacitor plate
128
includes a lower N-type polysilicon layer
134
and an upper tantalum silicide (TaSi
2
) layer
136
. The TaSi
2
layer is formed by a conventional deposition technique, and is provided in order to increase the conductivity of the conductive lines used in the device. The gates of the various transistors of the integrated circuit device have the same tantalum silicide/polysilicon structure. Silicides using refractory metals other than tantalum are known in the art, including, e.g., titanium, molybedinum and tungsten. The use of a silicide of a refractory metal atop a polysilicon layer is hereinafter referred to as “silicided polysilicon”. The thicknesses of the various layers are not drawn to scale but generally depict the shapes and positions of the elements of the structure. The tunnel oxide
126
is ultrathin, typically being only about 65 Å to 70 Å thick. The silicided polysilicon layer
128
is typically about 3500 Å thick, with its component layers
134
and
136
being about 2000 Å and 1500 Å, thick respectively. The thickness of glass layer
132
is typically about 8000 Å.
Referring again to
FIG. 2
, a first silicided polysilicon layer includes a relatively large rectangular portion
140
and narrow fingers
142
and
144
, which extend from the large portion
140
. The relatively large re

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