EEPROM memory cell comprising a selection transistor with...

Details EEPROM memory cell comprising a selection transistor with... EEPROM memory cell comprising a selection transistor with...

1999-09-28

2001-04-24

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S266000, C438S283000

Reexamination Certificate

active

06221717

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an EEPROM memory cell comprising a selection transistor with threshold voltage adjusted by proper ionic implantation, and related manufacturing process.
2. Discussion of the Related Art
A non-volatile EEPROM memory cell includes a polysilicon floating gate that is superimposed on a layer of gate oxide, superimposed in turn on a properly doped silicon substrate, and a control gate also of polysilicon, superimposed on the floating gate and electrically insulated from the latter by means of an intermediate dielectric layer (usually ONO, with a possible thin layer of overlaid polysilicon).
The logic state of the cell is determined by the quantity of charge contained in the floating gate of the transistor. Traditional non-volatile memories are programmed in two logic states, a writing one and a reading one, in order to store one bit per cell. With EEPROM memories, the quantity of charge is altered by the flow of charges by tunnel effect through a thin layer of silicon oxide (tunnel oxide) that is interposed between the semiconductor substrate and the floating gate of the transistor, in an active region.
In FLOTOX EEPROM type memories, the floating gate extends laterally even beyond the tunnel oxide region.
A selection transistor, arranged in series, that can be made in various forms, for example, can be made of two superimposed layers of polysilicon, laid over the gate oxide with or without an interposed intermediate dielectric layer, or having a single polysilicon gate, is associated with the memory cell. In case an intermediate oxide layer is present between the two polysilicon layers, the selection transistor is structurally similar to the memory cell, and in any case it must provide for some short-circuit between the two polysilicon layers in opportune zones of the device. Generally there are also present other transistors that are part of the external circuitry.
EEPROM type non-volatile memory cells, usually made up of memory cells that are arranged by rows and columns in a matrix structure, allow electrically modifying the information contained in a cell of the matrix in the programming stage, both during the writing stage and during the erasing stage.
In addition, the information contained in each single cell can be modified in an independent way from the other cells. This feature is achieved by means of a selection transistor that is put in series with the transistor in which the information is stored. The selection transistor enables a determined cell that must be programmed or read.
The aforementioned memory cells can be made with an optimization of the available area, thanks to the application of manufacturing techniques that allow the self-alignment of the control gates and of the floating gates. Examples of such manufacturing processes are given by U.S. Pat. No. 4,766,088 and by EP-0,255,159, that solve even the possible problems connected with the undesirable holes in the silicon substrate as a consequence of etching stages for the definition of the transistor gates.
In the advanced processes in which the dimensions of the entire memory structure are considerably reduced, the threshold voltage of the selection transistor, which depends on the length of the transistor itself, becomes quite low. All this can create problems since it can be difficult that the selection transistor is off when one wishes that the relative cell is not selected. In the case of EEPROM memories, for example, there can be problems during the programming stage of a memory cell, when it is necessary that the cells belonging to a same column, but that must not be programmed, are not selected and therefore that the relative selection transistors are securely off, otherwise quite high currents can flow with consequent leakage problems.
The problem can be solved with a circuitry solution, but it is quite complicated as the same circuitry becomes much more complex.
The most effective solution seems to be the introduction of an implantation stage of the selection transistor, in order to increase the threshold voltage and to avoid the aforementioned problems. Such implantation, in the current manufacturing techniques for EEPROM memory devices, involves the introduction of an additional dedicated operation in the manufacturing process.
With reference to
FIGS. 1
to
4
, there are shown four stages of a CMOS process with DPCC flow (Double Polysilicon in Short Circuit) for the manufacturing of an EEPROM type memory cell, including also the selection transistor, and of a transistor of the external circuitry, according to the known art. After the growth of a gate oxide layer
2
on a silicon substrate
1
and the definition of a tunnel area
3
in correspondence of the future floating gate, a lower polysilicon layer
4
, an intermediate dielectric layer
5
(for example ONO) and a thin polysilicon layer
6
are deposited. At this point selective etching and removal of the thin polysilicon layer
6
and of the intermediate dielectric layer
5
below is carried out by means of a mask
15
, that leaves the portion destined to the matrix cell covered, so as to eliminate the above mentioned layers in the regions of the memory device in which it is intended to provide transistors of the external circuitry (FIG.
1
).
The next stage provides for an implantation of the circuitry transistors by means of a mask
16
in order to define their threshold voltage (Low Voltage Shift implantation). In the matrix there is no need for any mask since there is present the intermediate dielectric layer
5
which prevents the flow of the dopant (for example boron) (FIG.
2
).
Subsequently an upper polysilicon layer
7
and a silicide layer
8
are deposited on the entire device, and then a selective etching by means of a mask
17
and a consequent removal are carried out. An etching of this kind affects the silicide layer
8
, the upper polysilicon layer
7
and the thin polysilicon layer
6
in the matrix, while in the external circuitry it affects the silicide layer
8
and the two polysilicon layers
7
and
4
, as there is no intermediate dielectric layer
5
as in matrix (FIG.
3
).
At this point a self-aligned etching of the intermediate dielectric layer
5
and of the lower polysilicon layer
4
in the matrix is carried out by means of a double-resist mask
18
, so as to define the memory cell, including the selection transistor.
In
FIG. 5
there is shown a memory cell that is obtained through the aforementioned process stages, in which the floating gate transistor
20
and the selection transistor
21
, making up the cell itself, can be observed, and in addition an external circuitry transistor
22
is present. The two polysilicon layers of the selection transistor are short-circuited in opportune regions of the device.
In a thus structured process flow, a possible implantation of the selection transistor in order to obtain an increase of the threshold voltage involves the introduction of an additional step with a proper dedicated mask.
An object of the present invention is to provide an EEPROM memory cell comprising a selection transistor that is implanted so as to obtain an increase of the threshold voltage.
SUMMARY OF THE INVENTION
According to the present invention, this and other objects are attained by a manufacturing process for an integrated structure comprising at least one circuitry transistor and at least one non-volatile EEPROM memory cell with relative selection transistor, comprising at least a first stage of growth and definition of a gate oxide layer on a silicon substrate, a second stage of definition of a tunnel oxide region in said gate oxide layer, a third stage of deposition and definition of a first polysilicon layer on said gate oxide layer and on said tunnel oxide region, a fourth stage of growth and definition of an intermediate dielectric layer on said first polysilicon layer, a fifth stage of selective etching and removal of said dielectric intermediate layer in a region for said circuitry transistor, a sixt

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