Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1999-04-23
2000-12-05
Niebling, John F.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438258, 438275, H01L 21336
Patent
active
061566098
ABSTRACT:
The present invention relates to a method of manufacturing, in a P-type substrate including active areas separated by field oxide areas, heavily-doped stop-channel regions under portions of the field insulation areas, more lightly-doped P- and N-type areas meant to form MOS transistor wells, and heavily-doped N-type areas meant to form the first electrode of a capacitor, including the steps of performing a high energy N-type implantation in P-channel MOS transistor areas; performing a high energy P-type implantation in N-channel MOS transistor areas; performing a high energy P-type implantation in stop-channel areas and in capacitor areas; and performing a low energy N-type implantation, masked by the field oxide.
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French Search Report from French Patent Application 98 05628, filed Apr. 28, 1998.
Galanthay Theodore E.
Hack Jonathan
Morris James H.
Niebling John F.
STMicroelectronics S.A.
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