Edge triggered delay line, a multiple adjustable delay line...

Details Edge triggered delay line, a multiple adjustable delay line... Edge triggered delay line, a multiple adjustable delay line...

1998-03-25

2001-01-16

Chin, Stephen (Department: 2734)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S354000, C327S161000, C327S263000, C327S276000, C327S277000, C327S284000

Reexamination Certificate

active

06175605

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to programmable delay lines, and more particularly to delay lines that are activated by edge transitions of input signals, and to delay line circuits that have multiple adjustable delay lines.
DESCRIPTION OF RELATED ART
Delay lines and silicon delay circuits are well known in the art. Delay lines generally are circuits composed of resistors, capacitors and/or inductors coupled to semiconductor amplifiers or buffers. The signal at the output of the delay line will be delayed by a period of time determined by the reactances of the resistive, capacitive, and/or inductive circuit. Silicon delay lines for digital signals such as clocks, as implemented on integrated circuits, are often formed of a chain of simple inverter circuits. The total delay of the chain of inverters will be the composite delay of the individual inverter circuits. The outputs of individual inverters or groups of inverters maybe the input to buffer circuits to provide multiple delayed outputs for the silicon delay line.
If an application requires a single delayed output that can be adjustable, a multiplexing logic circuit is connected to each of the outputs of the delay line. The select input of the multiplexing logic circuits will determine the input of the delay line and the output of the multiplexing logic circuit.
An application of delay lines composed of chains of inverters is the synchronizing of clocks internal to an integrated circuit with external system clocks. Two techniques for synchronizing internal clocks to external clocks are the latched type clock synchronized delay circuit (CSD) and the synchronous mirror delay circuit (SMD). The latched type clock synchronized delay circuit as described in “A1 ps Jitter 2 Clock Cycle Lock Time CMOS Digital Clock Generator Based On An Interleaved Synchronous Mirror Delay Scheme” T. Saeki, H. Nakamura, and J. Shimizu, Digest of Technical Papers—Symposium on VLSI Circuit, IEEE, 1997, is shown in FIG.
1
. The input buffer
10
receives the external system clock
5
. The input buffer
10
will have a delay factor designated d
1
. The output
15
of the input buffer
10
will be a first timing clock X
0
that is the input to a fixed delay line
20
. The fixed delay line
20
will have a delay that is a second delay factor (d1+d2). The delay of the fixed delay line will be determined generally by the delay of a plurality of serially cascaded inverters. The delay of each inverter will generally be on the order of 10-20 ps.
The output
25
of the fixed delay line
20
will be a second timing clock X
1
and is the input of the measurement delay line
30
. The measurement delay line
30
will be comprised of a plurality of delay elements
30
a
,
30
b
, . . . ,
30
x
, . . . ,
30
n
typically are individual stages of a shift register with a control gate. Each delay element
30
a
,
30
b
, . . . ,
30
x
, . . . ,
30
n
has an output
35
that is connected to the latch array
40
. The latch array
40
has a plurality of parallel latches
40
a
,
40
b
, . . . ,
40
x
, . . . ,
40
n
. When the delayed signal from the measurement delay line
30
has aligned with a second pulse of the first timing clock
15
, the latch
40
x
will be triggered.
Each output
45
of the plurality of latches
40
a
,
40
b
, . . . ,
40
x
, . . . ,
40
n
will be connected to the variable delay line
50
. The variable delay line
50
will have a plurality of serially cascaded delay elements
50
a
,
50
b
, . . . ,
50
x
, . . . ,
50
n
. The first timing signal
15
will transferred through each of the serially cascaded delay elements
50
a
,
50
b
, . . . ,
50
x
, . . . ,
50
n
until it reaches the selected delay element
50
x
that is gated by the latch
40
x
. The output
55
of the variable delay line
50
is the third timing signal X
3
and will be the input to the internal buffer
60
. The internal buffer
60
will amplify and buffer the third timing signal
55
for transmission to the internal circuitry of the integrated circuit.
The delay of the internal buffer
60
is designated d
2
, thus the delay of the fixed delay line
20
will be the sum of the delay of the input buffer
10
and the delay of the internal buffer
60
. The measured delay time &tgr;
m
from the measurement delay line
30
will be the difference of the clock period &tgr;
ck
of the external system clock
5
and the second delay factor (d1+d2) of the fixed delay line
20
. That is:
&tgr;
m
=&tgr;
ck
−(d1+d2).
The time to determine the measured period &tgr;
m
will be in the first cycle of the external system clock
5
. The synchronization will occur in the second cycle. The variable delay line
50
will delay the first timing signal
15
by the measured period of time &tgr;
m
. This will make the internal clock
65
synchronized with the external system clock
5
after two cycles from activation.
The synchronous mirror delay circuit, as described in T. Saeki, H. Nakamura, and J. Shimizu and “A 2.5 ns clock access 250 Mhz 256 Mb SDRAM with a synchronous mirror delay”, T. Saeki et al., IEEE International Solid State Circuits Conference, Paper # SP23.4, p. 374-375, 1996 is shown in FIG.
2
. The external system clock
105
is the input of the input buffer
110
. The delay time of the input buffer
110
will designated the first delay factor d1.
The output
115
of the input buffer
110
will be the first timing signal X
0
and is connected to the fixed delay line
120
. The output
125
of the fixed delay line
120
will be a second timing signal X
1
and will be delayed from the first timing signal
115
by a second delay factor d1+d2.
The second timing signal
125
will be the input to the measurement delay line
130
. The measurement delay line
130
is composed of a plurality of serially cascaded delay elements
130
a
,
130
b
, . . . ,
130
x
, . . . ,
130
n
. As with the latched-type clock synchronized delay circuit, each delay element is a stage of a shift register with control gates. Each delay element
130
a
,
130
b
, . . . ,
130
x
, . . . ,
130
n
has an output
135
that is connected to the transfer gate array
140
.
The transfer gate array
140
is composed of a plurality of transfer gates
140
a
,
140
b
, . . . ,
140
x
, . . . ,
140
n
. The first timing signal
115
is connected to each of the transfer gates. When the delayed second timing signal
135
has been delayed by an amount that will align the first cycle of the delayed second timing signal
135
with a second cycle of the first timing signal
115
, one of the transfer gates
140
x
will be activated. The delayed second timing signal
135
will be transferred through the selected transfer gate
140
x
to the variable delay line
150
. The measured delay time &tgr;
m
from the measurement delay line
130
is the difference of the clock period &tgr;
ck
of the external system clock X
0
105
and the delay factor (d
1
+d
2
) of the fixed delay line
120
. That is:
&tgr;
m
=&tgr;
ck
−(d
1
+d
2
)
The variable delay line
150
has a plurality of serially connected delay elements
150
a
,
150
b
, . . . ,
150
x
, . . . ,
150
n
. Each delay element
150
a
,
150
b
, . . . ,
150
x
, . . . ,
150
n
has an input that is connected to the output
145
of the transfer gate array
140
. The one transfer gate
140
x
that is activated when the first pulse of the delayed second timing signal
135
is aligned with the first timing signal
115
, is connected to the delay element
150
x
. The transferred delayed second timing signal
145
will be transferred and delayed through the variable delay line to form the third timing signal X
3
155
. The delay time through the variable delay line
150
is the same as the measured delay time &tgr;
m
. That is:
&tgr;
m
=&tgr;
ck
−(d
1
+d
2
)
The third timing signal
155
is the input to the internal buffer
160
. The internal buffer
160
will amplify, buffer, and delay the third timing signal
155
to form the internal clock
165
. The delay of the internal buffer will be a third delay fact

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