Metal treatment – Barrier layer stock material – p-n type – With contiguous layers of different semiconductive material
Reexamination Certificate
1998-02-19
2001-06-12
Chaudhari, Chandra (Department: 2813)
Metal treatment
Barrier layer stock material, p-n type
With contiguous layers of different semiconductive material
Reexamination Certificate
active
06245161
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the manufacture of substrates. More particularly, the invention provides a technique for manufacturing a silicon-on-silicon substrate assembly. The assembly consists of two substrates that are bonded together for use in the fabrication of a hybrid substrate for semiconductor integrated circuits, for example. However, it will be recognized that the invention has a wider range of applicability. For example, it can also be applied to other substrates for multi-layered integrated circuit devices, three-dimensional packaging of integrated semiconductor devices, microelectromechanical systems (“MEMS”), sensors, actuators, solar cells, biological and biomedical devices, and the like.
Wafers for electronic device fabrication are often cut from an ingot, or boule, of material with an abrasive saw. The wafer often serves as both a mechanical support and semiconductor material to form electronic devices in or on. One of the most common examples of this is cutting silicon wafers from a silicon ingot. The wafers are typically polished to a very fine surface finish after “lapping” the wafer to remove the mechanical damage left by the abrasive saw, and after “backlapping” the other side of the wafer to remove saw damage and to produce a wafer of the desired thickness, or to intentionally introduce strain in the wafer that improves the “gettering” of impurities. Gettering typically involves providing a trapping site for certain mobile impurity species that can degrade the performance of the devices in the integrated circuit. The impurities diffuse, or migrate, to the gettering sites, where they are trapped, thus lowering their concentration in the area of the devices.
In some processes, devices are fabricated directly in or on the silicon wafer. In other processes, a layer of semiconductor material is grown, for example by epitaxy, on the wafer. An epitaxial layer may provide lower impurity concentrations, or be of a different semiconductor type than the wafer. The devices are formed in what is known as the “active” layer, which is typically only a few microns thick.
Unfortunately, epitaxial layers have some associated problems that can affect wafer yield and device performance. Epitaxial layers that are grown on a substrate typically adopt the crystalline structure of the substrate. In most cases, the substrate is a single crystal of a particular orientation. However, the most favored crystallographic orientation for growing an epitaxial layer may not be the most favored crystallographic orientation for forming semiconductor devices. Additionally, surface defects or contamination on the surface of the substrate can lead to “pipes”, “spikes”, and other types of defects in the epitaxial layer. Often, a single defect will ruin a particular circuit, or cell, on a substrate. As the size of the cells get bigger and more complex, the chance that any particular cell will fail because of a defect in the epitaxy layer increases. The size of the cells generally increase, given a particular processing technology, as the device count increases, which usually indicates an increase in circuit complexity and functionality.
Another problem associated with epixatial layer configurations is the diffusion of doping species from the substrate to the epitaxial layer, or vice versa, and the autodoping of the epitaxial layer by doping species released by the substrate into the epitaxial growth environment. Unlike the mobile impurities that are trapped at gettering sites, doping species are typically introduced into the silicon crystal for a desired purpose. For example, the silicon substrate may have a high concentration of n-type impurities to reduce series resistance through the substrate, while the epitaxial layer has a low concentration of n-type impurities to allow efficient devices to be fabricated in the epitaxial layer. Alternatively, the substrate may be n-type impurities and the epitaxial layer may be p-type. In many applications it is desirable to have an abrupt junction between the epitaxial layer and the substrate; however, diffusion of the doping species across the interface degrades this abrupt junction.
Silicon epitaxy layers can be grown from a variety of sources, each with its own advantages and disadvantages. For example, silicon tetrachloride is typically used for growing epitaxial layers greater than 3 microns thick, but requires temperatures up to 1250° C., which results in significant autodoping and outdiffusion. Silane can be used to grow epitaxial layers around 1000° C., but it typically is used to grow only very thin layers, as it tends to pyrolyze and coat the chamber walls, requiring frequent cleaning. The rate of growth with silane is also much lower than with other sources, thus making it difficult to grow layers of epitaxial silicon more than about 1 micron thick.
The size of silicon wafers also continues to increase. Many state-of-the-art semiconductor devices are fabricated on 8-inch silicon wafers. Twelve-inch wafers are available, and the semiconductor fabrication industry is moving toward using wafers of this size, but, as with most changes in technology, the industry must solve some problems first. One of the problems is that growing a high-quality epitaxial layer on large wafers is very difficult. Some conventional processes do not have a sufficient yield of good wafers through the epitaxial growth process to make using a 12-inch wafer economically attractive, and even 8-inch wafer processes suffers from yield loss. These processes also generate a number of “scrap” wafers. The cost of a 12-inch substrate can be quite high, making yield loss and scrap generation very costly.
From the above, it is seen that a technique for providing an improved wafer that is cost effective is desirable.
SUMMARY OF THE INVENTION
According to the present invention, a technique for applying a thin film of material to a target wafer is provided. This technique separates thin films of material from a high-quality donor substrate by implanting particles, such as hydrogen ions, into the donor substrate, and then separating a thin film of the high-quality material above the layer of implanted particles. The thin film can be bonded to a lower-quality target wafer that provides mechanical support to form an economical hybrid substrate.
In a specific embodiment, the present invention provides a process for forming a film of material from a high-quality donor substrate using a controlled cleaving process. That process includes a step of introducing energetic particles (e.g., charged or neutral molecules, atoms, or electrons having sufficient kinetic energy) through a surface of a donor substrate to a selected depth underneath the surface, where the particles are at a relatively high concentration to define a thickness of donor substrate material (e.g., thin film of detachable material) above the selected depth.
The surface of the donor wafer is then attached to a target wafer using, a low-temperature bonding process to form an intermediate substrate assembly. The target wafer can be a single crystal, polycrystalline, or amorphous silicon substrate. Energy is applied to a selected region of the donor substrate material to initiate a controlled cleaving action in the donor substrate, whereupon the cleaving action is made using a propagating cleave front(s) to free the donor material, which adheres to the target wafer, from a remaining portion of the donor substrate. The thin film is then permanently bonded to the target wafer, typically with a high-temperature annealing process to form a hybrid silicon wafer suitable for integrated circuit fabrication, among other uses. The lower-cost, lower-quality target wafer portion of the hybrid silicon wafer provides the mechanical support for the hybrid wafer, while the thin film portion of the hybrid wafer provides a high-quality material for the formation of electronic devices.
In another embodiment, a layer of microbubbles is formed at a selected depth in a donor substrate, which is then bonded to a target
Cheung Nathan W.
Henley Francois J.
Chaudhari Chandra
Silicon Genesis Corporation
Thompson Craig
Townsend and Townsend / and Crew LLP
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