Static information storage and retrieval – Read/write circuit – Simultaneous operations
Reexamination Certificate
2000-03-10
2001-04-03
Mai, Son (Department: 2818)
Static information storage and retrieval
Read/write circuit
Simultaneous operations
C365S185090, C365S185220
Reexamination Certificate
active
06212105
ABSTRACT:
The present invention relates to EEPROM type memories (electrically erasable and programmable read-only memory).
In recent years, EEPROM type memories have undergone major development because of their advantageous characteristics. Indeed, these memories can be programmed or erased at will by the application of a high voltage Vpp, generally of 15 to 20 volts. Once programmed, they retain a piece of information indefinitely without having any electrical power supply. Owing to these properties, EEPROM type memories are the preferred means for recording identification data or transaction data in integrated circuits mounted on portable carriers such as, for example, the integrated circuits of chip cards or electronic tags.
However, integrated circuits of this kind are generally not protected against untimely cuts in supply voltage Vcc, which may occur at any time as the result of a handling error by the user (for example the fact of suddenly removing a chip card from the reader in which it is inserted) or poor power reception (especially when the supply voltage Vcc is received by electromagnetic induction).
Since the high programming or erasure voltage Vpp is generally produced from the supply voltage Vcc, an untimely cut in the voltage Vcc during a recording operation may lead to a loss of data during recording.
Indeed, the recording of a binary word in an EEPROM memory requires a step of erasing the previously recorded word and then a step of recording the new word by programming the cells of the memory at 0. This particular feature of a two-step recording is well known to those skilled in the art and is inherent in the internal arrangement, in word lines, of the memory cells where the cells of one and the same word line can be individually programmed at 0 but have to be erased collectively. It may be recalled that the programmed state of an electrically erasable and programmable memory cell is considered by convention to be the logic “0” and corresponds to the absence of electrons in a floating gate. The erased state corresponds to the logic “1” and to the storage of electrons in a floating gate.
Thus, for example, the recording of the word M equal to 00110101 at a memory address comprising the previous word M equal to 01001101 entails, first of all, the erasure of the previous word so that M is equal to 11111111 and then the programming at 0 of the bits with the place values 1, 3, 4 and 7 so that M is equal to 00110101.
In general, the supply voltage Vcc may get cut off during the recording of a binary word:
1) during the erasure of the previous word (entailing the risk of the recording of wrong data),
2) during the programming at 0 of the bits of the new word (with the risk of the recording of wrong words),
3) after the erasure of the previous word and before the programming at 0 of bits of the new word (in which case the new word as well as the previous word are irretrievably lost).
In the patent application WO 97/48100, the Applicant proposes an advantageous method to complete a programming or erasure operation in progress when there is a cut in the supply voltage Vcc. Briefly, this method consists firstly in maintaining the high voltage Vpp by a capacitor charge and, secondly, in maintaining the various electrical paths that lead the voltage Vpp to the memory cells. However, this method relates to cases 1) and 2) above and, in the case 3), does not make it possible to recover the lost word and carry out a programming operation.
Furthermore, in microprocessor-based integrated circuits, there are known ways of providing for a complex memory back-up system in software form that can be used to restore the memory in the event of a power cut. However, it is not possible, with this method, to recover the word that should have been recorded in the memory after the erasure of the former word. Furthermore, this method cannot be applied to wired-logic integrated circuits having no microprocessor (namely circuits such as memory cards, electronic tags, etc.). In these circuits, the problem is not managed and is considered to be an inherent drawback in the use of EEPROMs.
Finally, the application EP 618 591 and its equivalent U.S. Pat. No. 5,473,564 describe a method that bring into play an auxiliary cell associated with each word line of an “abacus” type of memory counter. The auxiliary cell makes it possible, after a cut in the supply voltage, to know that a bit of a most significant line has been programmed at 0 but that the line with a lower place value has not been properly erased at 1. This method specifically relates to the abacus-type counters of prepayment cards and does not resolve the general technical problem explained here above.
Thus, it is a goal of the present invention to provide for an EEPROM method and system making it possible to record a binary word in a secured manner with respect to the risks of a cut in the supply voltage.
Another goal of the present invention is to make it possible for this method and system to be implemented in a wired-logic circuit having no microprocessor.
Furthermore, the technical problem explained here above relates also to data counters made out of electrically erasable and programmable memory cells, for example memory card unit counters.
Thus, yet another goal of the present invention is to provide for a method and counter for the secured recording of a counting data element.
To achieve these goals, the idea of the invention is to provide for a method of fast recording in a single step that does not require the erasure of a word line before the recording of a binary word or a counting data element.
More particularly, the present invention proposes a method for recording a binary word by means of electrically erasable and programmable type memory cells organized in word lines, comprising a preliminary step of providing for at least two word lines that can be erased or programmed independently of each other and a first recording step comprising the steps of simultaneously selecting the two word lines, programming all or part of the memory cells of one of the word lines as a function of the binary word to be recorded and simultaneously erasing the other word line.
According to one embodiment, the method comprises a second recording step comprising the steps of simultaneously selecting the two word lines, erasing the word line programmed during the first recording step, programming all or part of the memory cells of the other word line as a function of the binary word to be recorded.
According to one embodiment, a first word line is selected in a first electrically erasable and programmable memory and a second word line is selected in a second electrically erasable and programmable memory.
According to one embodiment, the first and second memories comprise one and the same number of word lines and the two word lines are selected simultaneously in each of the memories by means of the same address.
According to one embodiment, one of the memories comprises a number of word lines smaller than the number of word lines of the other memory and the two word lines are selected simultaneously, in each of the memories, by means of the same address.
According to one embodiment, an electrically erasable and programmable warning cell is associated with each of the word lines of a memory, the warning cell of a word line is erased when the word line is programmed and the warning cell of a word line is programmed when the word line is erased.
According to one embodiment, the first recording step is performed alternately, at each new recording of a binary word, in one or the other of the word lines.
According to one embodiment, the binary word is a counting data element, the word lines are counting lines together forming a counter, the recording of a new counting data element is preceded by a step of comparing the new counting data element with a previously recorded counting data element, and the recording of the new counting data element is done only if the new counting data element is not different from the previous counting data element in to an authorize
Akin Gump Strauss Hauer & Feld L.L.P.
Inside Technologies
Mai Son
LandOfFree
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