Electronic digital logic circuitry – Interface – Logic level shifting
Patent
1994-04-05
1996-01-16
Westin, Edward P.
Electronic digital logic circuitry
Interface
Logic level shifting
326 18, 326 85, 326110, H03K 190175, H03K 19082, H03K 190948
Patent
active
054851068
ABSTRACT:
An efficient high-speed ECL to CMOS logic converter for BiCMOS integrated circuits. In one embodiment, a differential amplifier compares an ECL input signal to an ECL reference voltage and generates a pair of complementary intermediate signals on a corresponding pair of differential output nodes. The differential amplifier has two load resistors coupled in series with a common load resistor which limits the upper voltage swing at the differential output nodes. A regenerative stage coupled to the differential output nodes switches between a partially on state and a fully on state in response to the complementary intermediate signals. A pair of inverter stages convert the complementary intermediate signals into a pair of CMOS level signals. A pair of complementary output drivers coupled to the respective complementary inverter stages provide current driving capability. In this embodiment, each output driver includes a CMOS inverter pair and a bipolar transistor coupled between the respective output node of the driver and V.sub.DD.
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Bosnyak Robert J.
Drost Robert J.
Murata David M.
Santoro Mark R.
Tavrow Lee S.
Lim Kang S.
Santamauro Jon
Sun Microsystems Inc.
Westin Edward P.
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