ECL-to-CMOS buffer having a single-sided delay

Details ECL-to-CMOS buffer having a single-sided delay ECL-to-CMOS buffer having a single-sided delay

1992-07-06

1995-06-06

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36523008, 365194, 36518908, 365177, 365190, 3652556, 326 73, 326109, G11C 700, H03K 19092

Patent

active

054228484

ABSTRACT:
An ECL-to-CMOS buffer having a single-sided delay comprises an ECL logic gate, a level converter, a plurality of series connected inverters, and a NOR gate. The ECL logic gate receives an ECL level input signal, and provides complementary intermediate level logic signals. The level converter receives the intermediate level logic signals and provides a CMOS level output signal. The NOR gate receives the CMOS level output signal, via the series connected inverters, at an input terminal after a predetermined delay. One of the intermediate level logic signals is also received by the NOR gate at a second input terminal. The CMOS level output signal is delayed for a predetermined time in a low-to-high transition, with no unwanted delay in a high-to-low transition.

REFERENCES:
patent: 4645951 (1987-02-01), Uragami
patent: 4985865 (1991-01-01), Houston
patent: 4996671 (1991-02-01), Suzuki et al.
patent: 5022011 (1991-06-01), Allan
patent: 5216298 (1993-06-01), Ohba et al.
patent: 5313422 (1994-05-01), Houston
Nobuo Tamba et al., "An 8-ns 256K BiCMOS RAM", IEEE Journal of Solid-State Circuits, vol. 24, No. 4, Aug. 1989, FIG. 8, p. 1023.

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