ECL level/CMOS level logic signal interfacing device

Details ECL level/CMOS level logic signal interfacing device ECL level/CMOS level logic signal interfacing device

1997-02-19

1998-08-04

Westin, Edward P.

Electronic digital logic circuitry

Interface

Logic level shifting

326 34, 326 83, H03K 190185

Patent

active

057899410

DESCRIPTION:

BRIEF SUMMARY
The invention relates to an ECL level/CMOS level logic-signal interfacing device.
In current integrated circuits, especially logic circuits, it is essential to allow switching from a low logic level to a high logic level, or vice versa, within a small switching amplitude range.
In particular in so-called ECL (Emitter Coupled Logic) structures, the switching between low and high logic levels is defined between 3.2 V (low level) and 4.1 V (high level).
However, this type of circuit, which is being used more and more, poses the problem of the compatibility of these logic levels with the logic levels of the CMOS integrated circuits for which the low logic level is less than 1 V and the high logic level substantially equal to 5 V. The compatibility problem posed relates not only to the values of the supply voltages for these circuits but also to the continuity of transmission of the logic information because, especially, of the risk of ambiguity caused by the lack of discrimination between the ECL logic levels and the CMOS logic levels.
Various solutions have been proposed in a similar context relating to the lack of compatibility between BTL logic levels, low-voltage logic circuits, 1.1 V low logic level, 1.9 V high logic level and TTL (Transistor Transistor Logic) or CMOS. One envisaged solution within the aforementioned context may consist in generating a common threshold voltage, intermediate between the TTL and CMOS high logic level and low logic level, and in discriminating these logic levels from this threshold value.
This solution is satisfactory, but it has, however, the following drawbacks: threshold voltage and to discriminate between the aforementioned logic levels; in the form of an integrated circuit and corresponding occupation of silicon. Transposing such a solution to ECL logic circuits is therefore not to be desired because of the persistence of the aforementioned drawbacks.
The object of the present invention is to remedy these drawbacks by virtue of the use of an ECL/CMOS level logic-signal interfacing device in which the use of any common threshold voltage and of discrimination from this threshold voltage is dispensed with.
Another object of the present invention is also the use of an ECL/CMOS level logic-signal interfacing device in which the continuity of transmission of the logic information is provided by the use of transitions between voltage values of the low and high logic levels having compatible and gradually changing amplitudes.
The ECL level/CMOS level logic-signal interfacing device, the subject of the present invention, is noteworthy in that it comprises, connected in cascade and supplied with a CMOS level supply voltage relative to a reference voltage, a circuit for generating a signal in phase with the ECL level input signal, this in-phase signal having an amplitude greater than that of the input signal and a mean amplitude value greater than that of the ECL level input signal, a threshold inverter circuit, the threshold value of which is substantially equal to the mean amplitude value of the in-phase signal, this inverter circuit receiving on an inverting input the in-phase signal and delivering an inverted signal, a shaping inverter circuit receiving the inverted in-phase signal and delivering a calibrated in-phase signal and an output amplifier circuit receiving the calibrated in-phase signal and delivering an output signal, at the CMOS level, in phase with the input signal.
Such a device finds application in the manufacture of integrated circuits or of components for integrated circuits.
It will be more clearly understood on reading the description and on examining the drawings appended hereto, in which:
FIG. 1 represents a functional schematic diagram of the device which is the subject of the present invention;
FIG. 2a represents, by way of nonlimiting example, a diagram of one embodiment of the device which is the subject of the invention, according to FIG. 1, in CMOS technology.
FIGS. 2b1 to 2b4 represent signal timing diagrams obtained at the test points in FIG. 2a;
F

REFERENCES:
patent: 4968904 (1990-11-01), Yamashita et al.
patent: 5105107 (1992-04-01), Wilcox
patent: 5517148 (1996-05-01), Yin

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