Static information storage and retrieval – Read/write circuit
Reexamination Certificate
2008-05-06
2008-05-06
Dinh, Son (Department: 2824)
Static information storage and retrieval
Read/write circuit
C365S230030, C365S233100
Reexamination Certificate
active
07369444
ABSTRACT:
A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment of the present invention. The memory device comprises an interface for providing a first write address, a first write data, and a read address. A memory core is coupled to the interface and includes a first memory section having a first data path and a first address path and a second memory section having a second data path and a second address path. In an embodiment of the present invention, the first data and first address path is independent of the second data and second address path. The first write data is provided on the first data path responsive to the first write address being provided on the first address path while a read data is provided on the second data path responsive to the read address being provided on the second address path.
REFERENCES:
patent: 4184051 (1980-01-01), Clingenpeel
patent: 5185863 (1993-02-01), Hamstra
patent: 5245572 (1993-09-01), Kosonocky et al.
patent: 5361343 (1994-11-01), Kosonocky et al.
patent: 5367494 (1994-11-01), Shebanow
patent: 5631343 (1997-05-01), Binns et al.
patent: 5748539 (1998-05-01), Sproull et al.
patent: 5778419 (1998-07-01), Hansen et al.
patent: 5893927 (1999-04-01), Hovis
patent: 5893929 (1999-04-01), Shadan et al.
patent: 6018478 (2000-01-01), Higuchi
patent: 6044429 (2000-03-01), Ryan et al.
patent: 6091660 (2000-07-01), Sasaki et al.
patent: 6128728 (2000-10-01), Dowling
patent: 6178132 (2001-01-01), Chen et al.
patent: 6243799 (2001-06-01), Chan
patent: 6314046 (2001-11-01), Kamiya et al.
patent: 6343352 (2002-01-01), Davis et al.
patent: 6401167 (2002-06-01), Barth et al.
patent: 6636935 (2003-10-01), Ware
patent: 6640292 (2003-10-01), Barth et al.
patent: 6789175 (2004-09-01), Ryan et al.
patent: 6807590 (2004-10-01), Carlson et al.
patent: 7058863 (2006-06-01), Kouchi et al.
patent: 2002/0018394 (2002-02-01), Takahashi
patent: 2002/0087750 (2002-07-01), Yi
patent: 0430051 (1991-06-01), None
patent: 0833342 (1998-04-01), None
patent: 0833343 (1998-04-01), None
Final Office Action, United States Patent & Trademark Office, U.S. Appl. No. 10/442,352 filed on May 21, 2003, Sep. 4, 2007.
Response to Final Office Action, U.S. Appl. No. 10/442,352 filed on May 21, 2003, Oct. 24, 2007.
Perego Richard E.
Ware Frederick A.
Dinh Son
Rambus Inc.
Vierra Magen Marcus & DeNiro LLP
LandOfFree
Early read after write operation memory device, system and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Early read after write operation memory device, system and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Early read after write operation memory device, system and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2794537