Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-08-01
2004-11-30
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S583000, C438S630000, C438S649000, C438S651000, C438S655000
Reexamination Certificate
active
06825088
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and the method of manufacturing the device, and the invention particularly relates to a semiconductor device in which a memory device (memory cell part) and a logic circuit (logic part) are hybrid and the method of manufacturing the device.
2. Description of the Prior Art
In general, in a semiconductor device in which a memory device and a logic circuit are hybrid, a system LSI in which a DRAM is used as a memory device is referred to as an embedded DRAM (eRAM). In order to enhance the speed of the eRAM, a silicide layer, for instance, a CoSi
2
layer is formed over the diffused layer thereof in the process of manufacturing the eRAM.
FIGS. 10A-C
,
11
A-C, and
12
show schematic sectional process views in the method of manufacturing a semiconductor device such as a conventional eRAM. In the figures are shown active region
11
, isolation area
12
, gate oxide film (SiO
2
)
13
, polysilicon layer
14
, tungsten silicide layer (WSi layer)
15
, oxide film
16
of TEOS and the like, gate wiring
17
, silicon nitride film (SiN film)
18
, side wall
19
, cobalt silicide layer (CoSi
2
layer)
20
, oxide film
21
serving as an interlayer insulation film or dielectric (e.g., TEOS), contact hole
22
, plugs
23
and
28
, upper electrode
24
a
, lower electrode
24
b
, insulation film
24
c
, oxide films
26
and
27
, and metal wiring
29
.
Hereinafter, the method of manufacturing the conventional semiconductor device will next be described, referring to
FIGS. 10A-12
.
First of all, an area in which the part of a DRAM memory cell is formed (referred to as DRAM-forming area, hereinafter) and an area in which the part of logic is formed (referred to as logic-forming area, hereinafter) have been disposed on a semiconductor substrate (silicon substrate) as a base. In the DRAM-forming area and the logic-forming area, active region
11
and isolation area
12
are formed as underlayers, and over the underlayers, gate oxide film
13
, polysilicon layer
14
serving as a gate electrode, and tungsten silicide layer
15
are successively formed by means of deposition. Then, for instance, oxide film
16
such as TEOS is deposited over WSi layer
15
(FIG.
10
A).
After that, a gate wiring layer formed as mentioned above is patterned, to thereby form gate wiring
17
(FIG.
10
B). A N-diffused layer and a P-diffused layer (not shown) are formed by means of ion implantation process, and then in order to form a gate sidewall, silicon nitride film (SiN film)
18
is deposited all over the surface (FIG.
10
C).
In addition, the logic-forming area is processed by means of photolithographic processing and anisotropic etching, to thereby etch (etch back) the silicon nitride film and form sidewall
19
(FIG.
11
A). Ion implantation is performed to form a P+ diffused layer and a N+ diffused layer (not depicted).
In the logic-forming area, CoSi
2
layer
20
is formed over the source/drain diffused layer (FIG.
11
B). After depositing oxide film
21
becoming an interlayer insulation film in the DRAM-forming area and the logic-forming area, contact holes
22
connected with the source/drain diffused layer and the gate wiring is formed in both the DRAM-forming area and the logic-forming area by means of photolithographic processing and etching (FIG.
11
C).
After that, plugs
23
are formed within contact holes
22
, and simultaneously capacitors
24
are formed such that the capacitors are connected with right and left plugs
23
in the DRAM-forming area (capacitors
24
consist of upper electrode
24
a
and lower electrode
24
b
, and insulation films
24
c
are placed between upper electrode
24
a
and lower electrode
24
b
.). Subsequently, oxide films
26
and
27
are successively deposited over oxide film
21
in the DRAM-forming area and the logic-forming area; contact holes connected with plugs
23
are formed in oxide films
26
and
27
; and plugs
28
are formed in these contact holes. In addition, metal wirings
29
connected with plugs
28
are formed on oxide film
27
(FIG.
12
). Thereby, a semiconductor device so-called eRAM in which a DRAM memory cell part and a logic part are hybrid can be formed as shown in FIG.
12
.
Because the conventional semiconductor device and the method of manufacturing the device have been arranged as mentioned above, there have been the following drawbacks.
That is, CoSi
2
layer
20
is formed over the source/drain diffused layer in the logic part of the eRAM and the like in order to reduce the contact resistance. In a LSI such as an eRAM, with recent development of microfabrication and high-speed of devices, the accuracy of microfabrication (for instance, to ensure the accuracy of alignment when forming the contact) has been required and simultaneously the reduction of the resistance of the diffused layer (source/drain diffused layer) and the wiring (gate wiring) has been required. However, although in the conventional eRAM, the reduction of the contact resistance of the source/drain diffused layer in the logic part is considered, the reduction of the contact resistance in the memory cell part of a RAM is not considered. Furthermore, in the logic part, the reduction of the resistance of the gate wiring is not considered.
Thus, in the conventional semiconductor device, it is difficult to reduce the contact resistance of the source/drain diffused layer in the memory cell part of the RAM, and in addition, it is difficult to reduce the contact resistance of the gate wiring also in the logic part. For this reason, with recent development of microfabrication of devices, there have been various drawbacks in high-speed operations of devices caused by the high contact resistance.
Because the conventional semiconductor device is arranged as mentioned above, there has been a drawback that the reduction of the contact resistance is difficult in the source/drain diffused layer of the RAM memory cell part and the gate wiring of the logic part, and that the operation of the device at high speed is difficult with increase of microfabrication of devices.
SUMMARY OF THE INVENTION
The present invention has been accomplished to solve the above-mentioned drawbacks. An object of the present invention is to provide a semiconductor device in which a circuit can operate at high speed even if the device is microfabricated because of the reduction of the contact resistance and the wiring resistance in the source/drain diffused layer of the memory cell part and in the gate wiring of the logic part, and to provide a method of manufacturing the semiconductor device.
According to a first aspect of the present invention, there is provided a semiconductor device having a memory cell part and a logic part formed in a semiconductor substrate, wherein in the memory cell part a cobalt silicide layer is formed at least over the source/drain diffused layer of the part, and in the logic part a cobalt silicide layer is formed over the source/drain diffused layer of the part, and the gate wiring of the part includes a cobalt silicide layer.
Therefore, the contact resistance of the source/drain diffused layers in the memory cell part and the logic part can be reduced, and the wiring resistance of the gate wiring in the logic part can be also reduced, resulting in performing high-speed circuit operations even if the semiconductor device is further microfabricated.
According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device in which a memory cell part and a logic part are formed in a semiconductor substrate, the method including: a first step in which a gate wiring is formed serving as a first gate wiring in a first area in which the memory cell part is formed and a gate wiring is formed serving as a second gate wiring in a second area in which the logic part is formed, and a second step in which a cobalt silicide layer is formed over a source/drain diffused layer in the first area and a cobalt silicide layer is for
Sato Hidenori
Sogo Yasunori
Burns Doane Swecker & Mathis L.L.P.
Nelms David
Renesas Technology Corp.
Tran Long
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