Dynamically operated structured logic array

Details Dynamically operated structured logic array Dynamically operated structured logic array

1980-09-09

1983-11-22

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Precharge

365230, G11C 1300

Patent

active

044173270

ABSTRACT:
A clocked structured logic array functions in a dynamic, rather than static, mode of operation. The column output conductors and row conductors of the array are precharged to a predetermined voltage level at the beginning of a clock cycle. At the termination of a first phase of the clock cycle, the column conductors are selectively discharged in accordance with information stored in column memory elements. Upon termination of a second phase of the clock cycle, the row conductors are selectively discharged in accordance with a predetermined program, and responsive to the states of the column output conductors. The states of the row conductors are selectively transmitted to the column input conductors, and during a third phase of the clock cycle the information related to the states of the input conductors is transmitted to the memory elements.

REFERENCES:
patent: 3909631 (1975-09-01), Kitagawa

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