Dynamically loadable pattern history tables in a multi-task micr

Electrical computers and digital processing systems: processing – Processing control – Branching

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712240, 712233, 712 32, G06F 1500

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active

061087750

ABSTRACT:
A microprocessor (10) and a system (300) incorporating the same is disclosed, in which branch prediction is effected in response to the type of program in which branching instructions are contained. A fetch unit (26) includes a branch target buffer (56) and a plurality of pattern history tables (53). Select logic (80) receives signals indicating, for each branching instruction, the type of program containing the instruction, and selects one of the pattern history tables (53) for use in generating a prediction code in response to a portion of a branch history field (BH) in an entry (63) of the branch target buffer (56) corresponding to the instruction address. Disclosed examples of the signals used in selecting the pattern history table (53) include an indication (U/S) of the privilege level (e.g., user-level or supervisor-level) of the instruction. In the event of a task switch, the contents of one or more of the pattern history tables (53) may be stored in the task state segment (90) corresponding to an interrupted task, with the pattern history tables (53) loaded with entries from the task state segment (90) of the new task. In this way, each task may maintain its own branch pattern history-based prediction information when microprocessor (10) is operated in a multitasking environment.

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