Dynamically adaptable memory

Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator

Reexamination Certificate

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Details

C365S194000

Reexamination Certificate

active

06999354

ABSTRACT:
In an environment wherein a microprocessor can operate at several different voltage levels depending upon the instantaneous throughput of the microprocessor, a memory and memory adjustment circuit that permits operating the memory at a plurality of voltages in response to the microprocessor is disclosed. The memory and memory adjustment circuit sense the instantaneous operating voltage of the microprocessor and adjust the operating voltage of the memory in response thereto. The memory adjustment circuit more particularly increases or decreases the memory's bitline sense interval in response respectively to a decrease or increase in the memory's operating voltage.

REFERENCES:
patent: 6327202 (2001-12-01), Roohparvar
patent: 6724679 (2004-04-01), Nagasawa et al.
patent: 6795906 (2004-09-01), Matsuda
patent: 6804153 (2004-10-01), Yoshizawa et al.
patent: 6873555 (2005-03-01), Hiraki et al.

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