Electronic digital logic circuitry – With test facilitating feature
Reexamination Certificate
2011-03-29
2011-03-29
Tran, Anh Q (Department: 2819)
Electronic digital logic circuitry
With test facilitating feature
C326S009000, C326S033000
Reexamination Certificate
active
07915910
ABSTRACT:
In one embodiment, an integrated circuit includes a self calibration unit configured to iterate a test on a logic circuit in the integrated circuit at respectively lower supply voltage magnitudes until the test fails. A lowest supply voltage magnitude at which the test passes is used to generate a requested supply voltage magnitude for the integrated circuit. In an embodiment, an integrated circuit includes a series connection of logic gates physically distributed over an area of the integrated circuit, and a measurement unit configured to launch a logical transition into the series and detect a corresponding transition at the output of the series. The amount of time between the launch and the detection is used to request a supply voltage magnitude for the integrated circuit.
REFERENCES:
patent: 5440520 (1995-08-01), Schutz et al.
patent: 5682118 (1997-10-01), Kaenel et al.
patent: 5712589 (1998-01-01), Afek et al.
patent: 5856766 (1999-01-01), Gillig et al.
patent: 6078634 (2000-06-01), Bosshart
patent: 6154095 (2000-11-01), Shigemori et al.
patent: 6157247 (2000-12-01), Abdesselem et al.
patent: 6188252 (2001-02-01), Kawakami
patent: 6366157 (2002-04-01), Abdesselem et al.
patent: 6664775 (2003-12-01), Clark et al.
patent: 6762629 (2004-07-01), Tam et al.
patent: 6809606 (2004-10-01), Wong et al.
patent: 6874083 (2005-03-01), Sarangi et al.
patent: 6903964 (2005-06-01), Nahas et al.
patent: 7071768 (2006-07-01), Abe et al.
patent: 7084710 (2006-08-01), Huang et al.
patent: 7276925 (2007-10-01), Dobberpuhl et al.
patent: 7319358 (2008-01-01), Senthinathan et al.
patent: 7652494 (2010-01-01), Dobberpuhl et al.
patent: 2003/0206071 (2003-11-01), Wong et al.
patent: 2005/0188230 (2005-08-01), Bilak
patent: 2005/0206463 (2005-09-01), Godambe et al.
patent: 2005/0283630 (2005-12-01), Shikata
patent: 2006/0074576 (2006-04-01), Patel et al.
patent: 2006/0259840 (2006-11-01), Abadeer et al.
patent: 2009/0016140 (2009-01-01), Qureshi et al.
Vincent Von Kaenel, et al., “A Voltage Reduction Technique for Batter-Operated System,” IEEE Journal of Solid-State Circuits, vol. 25, No. 5, Oct. 19990, 5 pages.
Christopher Poirier, et al., “Power and Temperature Control on a 90nm Itanium-Family Processor,” 2005 IEEE International Solid-State Circuits Conference, 2 pages.
Tim Fischer, et al., “A 90nm Variable-Frequency Clock System for a Power-Managed Itanium-Family Processory,” 2005 IEEE International Solid-State Circuits Conference, 3 pages.
“CVD Circuit and Operation,” ISSCC 2005, Paper 16.2, ISSCC Visuals Supplement, p. 617.
“Impact of Double Switch Scheme,” ISSCC 2005, Paper 16.7, ISSCC Visuals Supplement, p. 623.
U.S. Appl. No. 11/753,853 filed May 25, 2007.
Office Action from U.S. Appl. No. 12/634,373, mailed on Aug. 5, 2010, 11 pages.
Search Report from PCT/US2010/021840 mailed on May 12, 2010, 7 pages.
Apple Inc.
Merkel Lawrence J.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Tran Anh Q
LandOfFree
Dynamic voltage and frequency management does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dynamic voltage and frequency management, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamic voltage and frequency management will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2674464