Dynamic type semiconductor memory device

Details Dynamic type semiconductor memory device Dynamic type semiconductor memory device

1984-03-09

1987-09-29

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365149, G11C 700, G11C 1124

Patent

active

046972528

ABSTRACT:
A dynamic type semiconductor memory device is disclosed, which comprises an n-type semiconductor layer, at least one memory cell having a capacitor for storing charges of an amount corresponding to a logic value and a first transistor having source and drain regions formed in the surface area of the p-type semiconductor layer and for transferring charges to and from the capacitor, a first drive circuit for applying a voltage to the gate of the first transistor through a word line, a second drive circuit for selectively applying a voltage of one of first and second levels through a bit line and the first transistor to the capacitor, and a bias circuit for applying a voltage to the substrate. The first transistor of the memory device is a p-channel transistor formed in the n-type semiconductor layer which is formed in the surface area of a p-type semiconductor layer. The bias circuit includes a charge pump section for setting the potential of the substrate at a third level lower than the first voltage.

REFERENCES:
patent: 3938109 (1976-02-01), Gionis et al.
patent: 4364075 (1982-12-01), Bohr et al.
patent: 4511811 (1985-04-01), Gupta
Chwang et al., "A 70ns High Density CMOS DRAM," IEEE International Solid-State Circuits Conference, ISSCC 83, pp. 56-57, 2/23/83.
Mano et al., "Submicron VLSI Memory Circuits," IEEE International Solid-State Circuits Conference, ISSCC 83, pp. 234-235, 2/25/83.

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