Dynamic type random-access memory having improved timing charact

Details Dynamic type random-access memory having improved timing charact Dynamic type random-access memory having improved timing charact

1990-05-15

1992-02-25

Bowler, Alyssa H.

Static information storage and retrieval

Read/write circuit

Precharge

365205, 365222, 365233, G11C 700, G11C 1141, G11C 11417, G11C 11419

Patent

active

050918850

ABSTRACT:
A dynamic type random-access memory includes a bit line pair constituted by first and second bit lines, a memory cell array constituted by a plurality of memory cells (MC.sub.i : i=0 to 255) connected to the bit line pair, a precharge circuit for precharging the bit line pair to a predetermined potential at a predetermined timing, a bit line sense amplifier to be enabled after data written in one of the plurality of memory cells (MC.sub.i : i=0 to 255) is read out to the bit line pair, and a charge transfer circuit connected between the bit line pair and first and second sense nodes of the bit line sense amplifier, turned off upon reception of a charge transfer drive signal which is decreased from a power source potential to a medium potential betwen the power source potential and a ground potential when a small potential difference is produced between bit lines of the bit line pair, and having an impedance decreased as a potential difference between the bit line pair and the first and second sense nodes of the bit line sense amplifier is increased when a potential difference between a control terminal and the first and second sense nodes exceeds a threshold value.

REFERENCES:
patent: 4852064 (1989-07-01), Kim et al.
patent: 4933905 (1990-06-01), Ootani

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