Dynamic substrate-coupled electrostatic discharging...

Details Dynamic substrate-coupled electrostatic discharging... Dynamic substrate-coupled electrostatic discharging...

2002-10-08

2003-08-26

Ngô, Ngân V. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S358000, C257S360000, C257S363000

Reexamination Certificate

active

06611028

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated electronic circuits. More particularly, this invention relates to circuits for protecting integrated circuits from damage caused by electrostatic discharge (ESD).
2. Description of Related Art
The electrostatic discharge (ESD) phenomena is well known in the art. As integrated circuit technologies have advanced, the destructive potential of ESD on VLSI chips has degraded the reliability of the VLSI chips. “ESD: A Pervasive Reliability Concern for IC Technologies,” by Duvvury et al., Proceedings of The IEEE, Vol. 81, No. 5, May 1993, provides an overview of ESD. The major source of ESD events are contact by the human body to integrated circuits. A typical work environment will accumulate a charge of about 0.16 &mgr;C induced to a body capacitance of 150 pf. This will lead to electrostatic potentials of 4 kV or greater. When the human body makes contact to an object such as an integrated circuit, peak currents of many amperes may flow for time periods of about 100 ns. The level of energy dissipated in such discharges is sufficient to cause breakdown or rupture of the oxide isolations or burnout of interconnections.
“The Impact of Technology Scaling on ESD Robustness and Protection Circuit Design,” by Amerasekera et al. (1), Proceeding EOS/ESD Symposium, 1994, pp. 237-245, discusses the concerns for protecting devices in deep submicron integrated circuit processes. These processes include thin oxides (40 Å-80 Å), small channel lengths (0.25 &mgr;m to 0.5 &mgr;m), shallow junctions (0.1 &mgr;m to 0.2 &mgr;m), and salicided diffusions. Further, as integrated circuit design has improved, the technologies have increased the number of input/output contact pads to greater than 300 and consequently the pad-to-pad spacing are now from 50 &mgr;m to 100 &mgr;m. The total area available for ESD protection circuits is now on the order of 2500 &mgr;m
2
, thus requiring the ESD protection circuits to be highly efficient.
“Modeling MOS Snapback and Parasitic Bipolar Action for Circuit-Level ESD and High-Current Simulations,” Amerasekera et al. (2), IEEE Circuits and Devices, Vol. 13, No. 2, Mary 1997, pp. 7-10, discusses mechanisms of operation of a metal oxide semiconductor (MOS) transistor. The MOS transistor as shown in
FIGS. 1
a
and
1
b
has an N-type drain
10
and an N-type source
15
diffused into a P-type semiconductor substrate
5
a gate electrode
20
is formed of the surface of a gate oxide
22
. The parasitic bipolar transistor
25
is formed by the drain
10
, the source
15
and the substrate
5
of the MOS transistor. The drain
10
acts as the collect of the parasitic transistor
25
. The emitter of the parasitic transistor
25
is the source
15
. The region between the source
15
and the drain
10
is the base of the parasitic bipolar transistor
25
. The bulk resistance of the P-type semiconductor substrate
5
is the base resistor R
sub
30
.
To characterize the performance voltage sources V
D
75
is connected to the drain
10
, V
s
80
is connected to the source, V
G
82
is connected to the gate
20
, and V
b
85
is connected to the P-type semiconductor substrate
5
.
FIG. 1
c
shows a plot of drain current I
D
60
versus the drain to source voltage (V
D
-V
s
) for various gate to source voltages (V
G
-V
s
) V
g1
, V
g2
, V
g3
, . . . , V
gn
. At the lower drain to source voltage (V
D
-V
s
) the MOS transistor will be operating in the linear region
110
or the saturation region
120
. However, as the drain to source voltage (V
D
-V
s
) increases, the drain current ID
60
increases and the MOS transistor enters the avalanche region
130
. Any further attempt to increase the drain to source voltage (V
D
-V
s
) will cause the MOS transistor to enter the snapback region
140
. Any further attempt to increase the drain to source voltage will cause dramatic increase in the drain current I
D
60
. The mechanism involved in the operation involves both avalanche breakdown and the turn on of the parasitic bipolar transistor
25
.
As the drain to source voltage (V
D
-V
s
) becomes sufficiently large, a high field region
35
near the drain generates a large amount of carries which result in a hole current I
sub
70
into the substrate
5
. The voltage drop across the substrate bulk resistance
30
raises the local substrate potential V′
B
72
. The voltage V′
B
72
causes the source
15
to substrate
5
junction to become forward biased. Electrons
45
injected from the source
15
to the substrate
5
are collected at the drain
10
. As the voltage drop across the substrate bulk resistance R
sub
30
becomes greater than 0.8V, the lateral bipolar transistor
25
begins to turn on.
The substrate current I
sub
70
is a function of the avalanche multiplication factor in the high field region
35
of the drain
10
. The avalanche generation current I
gen
95
provided by the current source
90
is a function of an incident current multiplied by the avalanche multiplication factor. If the gate voltage source V
G
82
is zero, the incident current is due solely to thermal generation and minority carrier diffusion. As the drain to source voltage is increased to the avalanche breakdown voltage the avalanche multiplication factor increases toward infinity.
A gate to source voltage V
G
82
greater than the threshold voltage V
TH
of the MOS transistor will result in a drain to source current I
DS
40
. A lower avalanche multiplication factor can now sustain the substrate current I
sub
70
. Hence, the parasitic bipolar transistor
25
turns on at a lower drain to source voltage (V
D
-V
s
). The level of the drain to source voltage (V
D
-V
s
) at which the parasitic bipolar transistor will turn on is now a function of the gate to source voltage VG
82
.
The snapback voltage
145
of
FIG. 1
c
is the voltage level of the drain to source voltage (V
D
-V
s
) at which any increase in the drain to source voltage (V
D
-V
s
) causes an inordinate increase in the drain current I
D
60
. “The Effect of Interconnect Process and Snapback Voltage on the ESD Failure Threshold of N-MOS Transistors,” by Chen, IEEE Transactions on Electron Devices, Vol. 35, No. 12, December, 1988, discusses the function of the ESD pass voltage versus the snapback voltage of an N-MOS transistor. The ESD pass voltage is the level of an ESD voltage source modeled after human body at which an N-MOS transistor can sustain without damage. As shown in
FIG. 2
, for N-MOS transistors fabricated with lightly doped drain (LDD), Graded Drain (GD), or Double Diffused Drain (DDD), the ESD pass voltage is almost linearly dependent on the snapback voltage of the N-MOS transistor. This indicates that a lower snapback voltage provides enhanced protection for integrated circuits from an ESD event.
Traditionally, ESD protection circuits have consisted of the MOS transistor of
FIG. 1
a
with the gate
20
connected directly to the source
15
and connected to a power supply voltage source that is either V
ss
or Ground. Alternately, the gate
20
connected to the drain
10
that is connected to the input/output contact pad. As discussed above, the snapback voltage is at a maximum value and the ESD pass voltage is at a minimum.
Amerasekera et al. (1) discusses gate coupled N-MOS ESD protection circuit. And N-MOS transistor has a drain connected to an input/output contact pad and a source connected to a substrate biasing voltage source V
ss
. The gate of the N-MOS transistor is coupled through capacitor to the input/output contact pad and through resistor to the substrate biasing voltage source V
ss
. When an ESD voltage source is connected to the input/output contact pad, the ESD voltage is coupled to the gate of the N-MOS transistor. The N-MOS transistor begins to conduct as described above and the snapback voltage is thus decreased.
U.S. Pat. No. 5,631,793 (Ker et al.) discloses a similar ESD protection circuit. The circuit consists of an N-MOS transistor configured as described above except the substrate bulk is

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