Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2007-08-31
2009-11-10
Phung, Anh (Department: 2824)
Static information storage and retrieval
Read/write circuit
Precharge
C365S207000
Reexamination Certificate
active
07616510
ABSTRACT:
The object of the present invention is to provide a DRAM, in which the operation speed for a sense amplifier can be increased. Bit line precharging circuits PCt and PCb are arranged to precharge bit lines BLt and /BLt to a ground voltage GND, and reference word lines RWLo and RWLe and reference memory cells RMC are arranged, so that when a word line WL is activated, a potential difference is always generated between the bit lines BLt and /BLt. The sources of transistors N10and N11of an N-type sense amplifier NSAt are connected directly to a ground terminal GND, and the sources of transistors P2and P3of a P-type sense amplifier PSA are connected directly to a power source VDD. The gates of the transistors N10and N11are connected to the bit lines /BLt and BLt, and the drains are connected to the bit lines BLt and /BLt, respectively. Shift word lines SWL and shift memory cells SMC are arranged, so that the N sense amplifier NSAt can amplify the potential difference between the bit lines BLt and /BLt.
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International Business Machines - Corporation
LeStrange Michael J.
Phung Anh
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