Dynamic semiconductor memory read/write access circuit

Details Dynamic semiconductor memory read/write access circuit Dynamic semiconductor memory read/write access circuit

1979-12-14

1980-12-09

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Precharge

307279, 365208, G11C 1140

Patent

active

042388414

ABSTRACT:
To the known sense latch already existing in a bit line pair in an FET memory, and to the two bit switches in each bit line another latch is arranged in series which furthermore is coupled to the common data input and output via a write driver on the one side and a read driver on the other. Both latches are of an identical structure and controlled by the same pulses in the read as well as in the write phase. The data path via the write driver and the read driver up to, or from, the additional latch is respectively designed as unidirectional double rail line, and selectively connectable via the bit switches with the bidirectional double rail line to the respective bit line pair.

REFERENCES:
patent: 3387286 (1978-06-01), Dennard
patent: 4053873 (1977-10-01), Freeman
patent: 4112512 (1978-09-01), Arzubi
patent: 4125878 (1978-11-01), Watanabe

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