Dynamic semiconductor memory device with high-speed serial-acces

Details Dynamic semiconductor memory device with high-speed serial-acces Dynamic semiconductor memory device with high-speed serial-acces

1991-06-07

1994-02-22

Mottola, Steven

Static information storage and retrieval

Read/write circuit

Multiplexing

36523002, G11C 800

Patent

active

052894134

ABSTRACT:
A MOS memory device includes an array of rows and columns of memory cells, word lines connected to the rows of memory cells, and a plurality of pairs of bits lines connected to the columns. Sense amplifiers and transfer gates are provided for every bit line pair. A column decoder has outputs connected via column-select lines to transfer gates such that each output is connected to two adjacent gates. When activating a certain column, the column decoder potentially activates another column adjacent to the certain column before actually receiving the corresponding column address. This permits information bits stored in four memory cells to be transferred simultaneously to the registers and latched therein. A multiplexer serially reads out the latched information bits. The column preactivation improves the serial accessing speed of the memory device.

REFERENCES:
patent: 4618947 (1986-10-01), Tran et al.
patent: 4800530 (1989-01-01), Itoh et al.
patent: 4899312 (1990-02-01), Sato
IEEE Journal of Solid-State Circuits, vol. 24, No. 4, Aug. 1989, pp. 900-904, K. Numata, et al., "New Nibbled-Page Architecture for High-Density DRAM's".
"A 4-Mbit CMOS SRAM with 8-NS Serial-Access Time"; Hirotada Kuriyama et al.; 1990 Symposium on VLSI Circuits; pp. 51-52.

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