Dynamic semiconductor memory device that can control through cur

Details Dynamic semiconductor memory device that can control through cur Dynamic semiconductor memory device that can control through cur

1996-01-22

1997-04-08

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36518901, 365222, 365228, 365233, G11C 1134

Patent

active

056194579

ABSTRACT:
A first logic gate circuit receives an internal row strobe signal, an internal column strobe signal and a self refresh mode for providing an operation state detection signal. The operation state detection signal attains an H level when in a stand-by state and a self refresh state. A second CMOS logic gate circuit is closed when the operation state detection signal attains an H level. Therefore, an external input/output control signal is not transmitted to the internal circuit, and a through current does not flow in the CMOS logic gate independent of the level of the external input/output control signal.

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