Dynamic semiconductor memory device having simultaneous operatio

Details Dynamic semiconductor memory device having simultaneous operatio Dynamic semiconductor memory device having simultaneous operatio

1993-01-21

1993-12-28

Dixon, Joseph L.

Static information storage and retrieval

Read/write circuit

Precharge

36523003, 365233, G11C 700, G11C 800

Patent

active

052745961

ABSTRACT:
A dynamic semiconductor device includes a plurality of dynamic memory cell arrays each having memory cells arranged in a matrix form, row decoders connected to the plurality of memory cell arrays, respectively, sense amplifiers connected to the plurality of memory cell arrays, respectively, a plurality of bit lines connected to the each of the plurality of memory cell arrays, for exchanging data with the memory cells arranged in the matrix form, the plurality of bit lines being connected to a corresponding one of the sense amplifiers, a plurality of word lines, intersecting the plurality of bit lines, for selecting the memory cells, the word lines selected by row addresses adjacent on a logical address plane being located in adjacent ones of the memory cell arrays, the word lines within the each memory cell array being selected by an upper row address of a row address output from a corresponding one of the row decoders, and means for selecting the memory cell arrays by a lower row address of the row address, the selecting means raising a plurality of given word lines selected by the addresses adjacent to a row address corresponding to any word line and enabling corresponding ones of the sense amplifiers of the memory cell arrays including the given word lines when the memory cells on the any word line are to be accessed.

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