Dynamic semiconductor memory device

Details Dynamic semiconductor memory device Dynamic semiconductor memory device

1998-10-21

2000-11-21

Dinh, Son T.

Static information storage and retrieval

Systems using particular element

Capacitors

365 51, 365 63, 36523003, G11C 1124

Patent

active

061512443

ABSTRACT:
Memory cell minimum units (MCU) formed of multi-bit one transistor/one capacitor type memory cells are repeatedly arranged in a column direction, and bit line contacts (BCT) are shifted in the column direction relative to a row direction. The bit line contacts are repeatedly shifted with a prescribed number of bit lines as a unit. A set of a read bit line onto which memory cell data are read and a reference bit line supplying a reference potential can be obtained by controlling the voltage of cell plate lines and bit lines for each set of bit lines. Accordingly, a memory cell occupation area can be reduced and sensing operation in the folded bit line arrangement is possible. Consequently, a memory cell occupation area per one bit can be dramatically reduced and sensing operation in the folded bit line arrangement can be performed.

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patent: 5815428 (1998-09-01), Tsuruda et al.
"A Staggered NAND DRAM array architecture for a Gbit scale integration", S. Shiratake et al., 1994 Symposium on VLSI Circuits Digest of Technical Papers, pp. 75-76.
"Cell-Plate-Line and Bit-Line Complementarily Sensed (CBCS) Architecture for Ultra Low-Power Non-Destructive DRAMs", T. Hamamoto et al., 1995 Symposium on VLSI Circuits Digest of Technical Papers, pp. 79-80.
"An Experimental DRAM with a NAND-Structured Cell", T. Hasegawa et al., IEEE Journal of Solid-State Circuits, vol. 28, No. 11, Nov. 1993, pp. 1099-1103.

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