Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Metastable state prevention
Reexamination Certificate
2002-06-04
2004-06-15
Tran, Anh Q. (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Metastable state prevention
C326S095000, C326S096000, C326S097000, C326S098000
Reexamination Certificate
active
06750677
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a dynamic semiconductor integrated circuit used in a decoder circuit such as a memory circuit and a matching detection circuit. In particular, the present invention relates to a technique for speeding up a semiconductor integrated circuit in which a NAND dynamic circuit is connected to a NOR dynamic circuit. Furthermore, the present invention relates to a circuit arrangement technique for preventing degradation of the transistor characteristics in such a semiconductor integrated circuit.
2. Description of the Related Art
In a decoder circuit such as a memory circuit that is synchronized with a clock, in order to increase speed, a NAND dynamic circuit has been used so as to reduce the number of logic stages and the capacity of a gate of a decoder circuit with a static configuration. In a matching detection circuit for comparing a plurality of data with each other to detect whether or not they are matched, used in a comparison portion of a translation lookaside buffer (TLB) and a tag part of a cache, in order to increase speed, a differential sense amplifier system for comparing voltage differences has been used. Examples of the sense amplifier system include circuit systems described in JP 10(1998)-27481 A and JP 2000-251479 A. The above-mentioned circuits are those of a latch type for holding data only in a logic “H” level period or a logic “L” level period of a clock.
Examples of a flip-flop circuit increasing speed, for holding output data of a decoder circuit or a matching detection circuit during one period of a clock, include those described in “A rue Single-Phase-Clock Dynamic CMOS Circuit Technique” (YUAN JI-REN et al.) in IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.SC-22, NO.5, OCTOBER 1987 and “A New Family of Semidynamic and Dynamic Flip-Flops with Embedded Logic for High-Performance Processors” (Fabian Klass et al.) in IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 5, MAY 1999.
In the case of the above-mentioned conventional configuration, along with miniaturization of a semiconductor, a power source voltage is lowered only with a NAND dynamic circuit. Therefore, in order to maintain speed increases, there is a limit to the number of serial stages. Furthermore, according to the method of YAN JI-REN et al. and Fabian Klass et al. in which a NAND dynamic circuit is connected to an output of a NOR dynamic circuit, when an input element of the NOR dynamic circuit is at a logic “L” level, during a period in which a clock transitions from a logic “L” level to a logic “H” level, an output node of the NOR dynamic circuit is in a floated state, an output of the NAND dynamic circuit of a subsequent stage becomes a logic “L” level, and a coupling capacitance formed between the output node of the NOR dynamic circuit and the NAND dynamic circuit holds a charge. Therefore, the output voltage of the NOR dynamic circuit is lowered, and the operation speed is degraded.
Furthermore, in the matching detection circuit using an analog element, when a device area is decreased, the variation in characteristics of an element is increased in accordance with a scaling rule of miniaturization, and an operation becomes unstable. On the other hand, when the operation of an element is stabilized, wiring and the like becomes long due to an increased area of a device, which makes it difficult to realize increased speed.
Another problem is caused along with miniaturization of a semiconductor. More specifically, when a shallow trench insulator (STI) is formed in a semiconductor substrate so as to separate transistors or circuit blocks, a lattice constant of a molecular structure that is a characteristic of a diffusion region constituting a source or a drain of a MOS transistor is distorted Because of this, stress is applied to the diffusion region of a transistor formed in a region close to the STI. Consequently, charge mobility is decreased, a current ability (Ids) is lowered, and a threshold voltage (V
th
) is increased. More specifically, the characteristics of transistors close to the STI and transistors, in which an interval of a diffusion capacity portion between the transistors is small, are degraded.
SUMMARY OF THE INVENTION
Therefore, with the foregoing in mind, it is an object of the present invention to provide a semiconductor integrated circuit in which increased speed is realized by a system in which a NAND dynamic circuit is connected to a NOR dynamic circuit, glitches occurring in an output of the NAND dynamic circuit are reduced to realize a stable operation and low power consumption, and transistor characteristics are prevented from being degraded by a miniaturization process.
In order to achieve the above-mentioned object, a first semiconductor integrated circuit of the present invention includes: a NOR dynamic circuit for receiving a first clock (CLK
1
) and a plurality of first data (ADR [
0
-
4
], holding a charge of a first output node in a case where during one of a period from rising to falling of the first clock and a period from falling to rising of the first clock, the first output node is charged, and during the other period, all the plurality of first data are matched with each other, and discharging the first output node in a case where at least one of the plurality of first data is not matched; a NAND dynamic circuit for receiving a second dock (CLK
2
, CLK
3
) and a signal from the first output node, holding a charge of a second output node in a case where during one of a period from rising to falling of the second clock and a period from falling to rising of the second dock, the first output node is discharged, and discharging the second output node in a case where the charge of the first output node is held; and a compensating circuit for compensating for a voltage drop of the first output node, which is caused by a coupling capacitance formed between the first output node and the second output node, which occurs when the second output node is discharged while the charge of the first output node is held
According to the above-mentioned configuration, the number of logic stages is reduced, compared with a decoder entirely composed of static circuits. Furthermore, due to the NAND dynamic circuit, compared with the case where a static NAND circuit is provided, the load capacity of a gate that receives a second dock and the load capacity of a gate of the NAND dynamic circuit connected to the output node of the NOR dynamic circuit are reduced. Furthermore, a voltage drop of the output node of the NOR dynamic circuit is compensated by the compensating circuit, whereby an operation speed can be increased.
In the first semiconductor integrated circuit, it is preferable that the compensating circuit includes a feedback circuit for charging the first output node in a case where the second output node is discharged.
According to the above-mentioned configuration, while a signal of the output node of the NAND dynamic circuit transitions from a logic “H” level to a logic “L” level, a voltage drop due to a coupling capacitance is compensated, and a voltage level of the output node of the NOR dynamic circuit can be increased, whereby increased speed can be realized.
In the first semiconductor integrated circuit, it is preferable that the NOR dynamic circuit includes: a first N-type MOS transistor in which a gate is supplied with the first clock and a source is grounded; a first P-type MOS transistor in which a gate is supplied with the first dock and a source is connected to a power source; and a plurality of second N-type MOS transistors in which gates are supplied with the plurality of first data, sources are connected to a drain of the first-N-type MOS transistor and drains are connected to a drain of the first P-type MOS transistor, whereby the first output node is formed.
According to the above-mentioned configuration, the number of serial stages of each transistor is two or less, and increased speed can be realized even at a low voltage.
In the first semiconductor integrated c
Matsushita Electric - Industrial Co., Ltd.
Tran Anh Q.
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