Dynamic resynchronization of clocked interfaces

Details Dynamic resynchronization of clocked interfaces Dynamic resynchronization of clocked interfaces

2006-12-19

2006-12-19

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

Using delay

C713S400000, C713S500000

Reexamination Certificate

active

07152176

ABSTRACT:
One or more methods and systems of resynchronizing or dynamically retuning a clock signal over a high speed clocked data interface are presented. In one embodiment, the system and method utilizes first and second delay lines, a first pair of digital logic devices to generate a first data sequence, a second pair of digital logic devices to generate a second data sequence, a memory, a set of software instructions resident in the memory, a processor, and a user interface. The first and second data sequences are input into a digital logic circuit that compares the two sequences and generates an output. The output is clocked into a digital logic device to generate an indicator signal that is used to resynchronize or dynamically re-tune the clock signal.

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patent: 2004/0239388 (2004-12-01), Lee

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